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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. h8/3834 series hardware manual 8 users manual rev.5.0 2003.05 h8/3837 hd6433837, hd6433837s, hd64473837 h8/3836 hd6433836, hd6433836s h8/3835 hd6433835, hd6433835s h8/3834 hd6433834, hd6433834s, hd6473834 h8/3833 hd6433833, hd6433833s h8/3832 hd6433832s notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. preface the h8/300l series of single-chip microcomputers has the high-speed h8/300l cpu at its core, with many necessary peripheral functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu. the h8/3834 series has a system-on-a-chip architecture that includes such peripheral functions as an lcd controller/driver, five types of timers, a 14-bit pwm, a three-channel serial communication interface, and an a/d converter. this makes it ideal for use in systems requiring an lcd display. this manual describes the hardware of the h8/3834 series. for details on the h8/3834 series instruction set, refer to the h8/300l series programming manual. note: the terms h8/3834, h8/3834s, and h8/3834 series used in the text refer to the products shown below. 1. h8/3834: hd6433837, hd6433836, hd6433835, hd6433834, hd6433833, hd6473837, hd6473834 2. h8/3834s: hd6433837s, hd6433836s, hd6433835s, hd6433834s, hd6433833s, hd6433832s 3. h8/3834 series: all products, including the h8/3834 and h8/3834s i contents section 1 overview ............................................................................................................ 1 1.1 overview .................................................................................................................... ........ 1 1.2 internal block diagram ...................................................................................................... 5 1.3 pin arrangement and functions ......................................................................................... 6 1.3.1 pin arrangement ................................................................................................... 6 1.3.2 pin functions......................................................................................................... 8 section 2 cpu ...................................................................................................................... 13 2.1 overview .................................................................................................................... ........ 13 2.1.1 features ................................................................................................................. 1 3 2.1.2 address space ....................................................................................................... 14 2.1.3 register configuration .......................................................................................... 14 2.2 register descriptions....................................................................................................... ... 15 2.2.1 general registers .................................................................................................. 15 2.2.2 control registers................................................................................................... 15 2.2.3 initial register values ........................................................................................... 17 2.3 data formats ................................................................................................................ ...... 17 2.3.1 data formats in general registers........................................................................ 18 2.3.2 memory data formats .......................................................................................... 19 2.4 addressing modes............................................................................................................ .. 20 2.4.1 addressing modes................................................................................................. 20 2.4.2 effective address calculation............................................................................... 22 2.5 instruction set ............................................................................................................. ....... 26 2.5.1 data transfer instructions ..................................................................................... 28 2.5.2 arithmetic operations ........................................................................................... 30 2.5.3 logic operations ................................................................................................... 31 2.5.4 shift operations .................................................................................................... 31 2.5.5 bit manipulations.................................................................................................. 33 2.5.6 branching instructions .......................................................................................... 37 2.5.7 system control instructions.................................................................................. 39 2.5.8 block data transfer instruction............................................................................ 40 2.6 basic operational timing .................................................................................................. 41 2.6.1 access to on-chip memory (ram, rom).......................................................... 41 2.6.2 access to on-chip peripheral modules................................................................ 42 2.7 cpu states.................................................................................................................. ........ 43 2.7.1 overview ............................................................................................................... 43 2.7.2 program execution state ....................................................................................... 45 2.7.3 program halt state ................................................................................................ 45 2.7.4 exception-handling state ..................................................................................... 45 ii 2.8 memory map.................................................................................................................. .... 46 2.8.1 memory map......................................................................................................... 46 2.8.2 lcd ram address relocation ............................................................................ 52 2.9 application notes........................................................................................................... .... 53 2.9.1 notes on data access............................................................................................ 53 2.9.2 notes on bit manipulation .................................................................................... 55 2.9.3 notes on use of the eepmov instruction ........................................................... 61 section 3 exception handling ........................................................................................ 63 3.1 overview .................................................................................................................... ........ 63 3.2 reset ....................................................................................................................... ............ 63 3.2.1 overview ............................................................................................................... 63 3.2.2 reset sequence...................................................................................................... 63 3.2.3 interrupt immediately after reset ......................................................................... 65 3.3 interrupts .................................................................................................................. .......... 66 3.3.1 overview ............................................................................................................... 66 3.3.2 interrupt control registers.................................................................................... 67 3.3.3 external interrupts................................................................................................. 75 3.3.4 internal interrupts.................................................................................................. 76 3.3.5 interrupt operations .............................................................................................. 76 3.3.6 interrupt response time ....................................................................................... 81 3.4 application notes........................................................................................................... .... 81 3.4.1 notes on stack area use ...................................................................................... 81 3.4.2 notes on rewriting port mode registers.............................................................. 82 section 4 clock pulse generators .................................................................................. 85 4.1 overview .................................................................................................................... ........ 85 4.1.1 block diagram ...................................................................................................... 85 4.1.2 system clock and subclock.................................................................................. 85 4.2 system clock generator..................................................................................................... 8 6 4.3 subclock generator .......................................................................................................... .. 88 4.4 prescalers.................................................................................................................. .......... 91 4.5 note on oscillators ......................................................................................................... .... 92 section 5 power-down modes ....................................................................................... 93 5.1 overview .................................................................................................................... ........ 93 5.1.1 system control registers...................................................................................... 96 5.2 sleep mode.................................................................................................................. ....... 99 5.2.1 transition to sleep mode ...................................................................................... 99 5.2.2 clearing sleep mode ............................................................................................. 99 5.3 standby mode ................................................................................................................ .... 99 5.3.1 transition to standby mode.................................................................................. 99 5.3.2 clearing standby mode ........................................................................................ 100 iii 5.3.3 oscillator settling time after standby mode is cleared ...................................... 100 5.3.4 transition to standby mode and port pin states .................................................. 101 5.4 watch mode .................................................................................................................. ..... 101 5.4.1 transition to watch mode .................................................................................... 101 5.4.2 clearing watch mode ........................................................................................... 102 5.4.3 oscillator settling time after watch mode is cleared ......................................... 102 5.5 subsleep mode ............................................................................................................... .... 102 5.5.1 transition to subsleep mode ................................................................................ 102 5.5.2 clearing subsleep mode ....................................................................................... 103 5.6 subactive mode.............................................................................................................. .... 103 5.6.1 transition to subactive mode ............................................................................... 103 5.6.2 clearing subactive mode...................................................................................... 103 5.6.3 operating frequency in subactive mode.............................................................. 103 5.7 active (medium-speed) mode............................................................................................ 104 5.7.1 transition to active (medium-speed) mode ......................................................... 104 5.7.2 clearing active (medium-speed) mode................................................................ 104 5.7.3 operating frequency in active (medium-speed) mode........................................ 104 5.8 direct transfer............................................................................................................. ....... 104 5.8.1 direct transfer overview...................................................................................... 104 5.8.2 calculation of direct transfer time before transition ........................................ 106 section 6 rom .................................................................................................................... 109 6.1 overview .................................................................................................................... ........ 109 6.1.1 block diagram ...................................................................................................... 109 6.2 h8/3834 prom mode ....................................................................................................... 110 6.2.1 setting to prom mode......................................................................................... 110 6.2.2 socket adapter pin arrangement and memory map............................................ 110 6.3 h8/3834 programming ....................................................................................................... 11 3 6.3.1 writing and verifying ........................................................................................... 113 6.3.2 programming precautions ..................................................................................... 117 6.4 h8/3837 prom mode ....................................................................................................... 118 6.4.1 setting to prom mode......................................................................................... 118 6.4.2 socket adapter pin arrangement and memory map............................................ 118 6.5 h8/3837 programming ....................................................................................................... 12 1 6.5.1 writing and verifying ........................................................................................... 121 6.5.2 programming precautions ..................................................................................... 126 6.6 reliability of programmed data ........................................................................................ 127 section 7 ram .................................................................................................................... 129 7.1 overview .................................................................................................................... ........ 129 7.1.1 block diagram ...................................................................................................... 129 section 8 i/o ports ............................................................................................................. 131 iv 8.1 overview .................................................................................................................... ........ 131 8.2 port 1 ...................................................................................................................... ............ 133 8.2.1 overview ............................................................................................................... 133 8.2.2 register configuration and description................................................................ 133 8.2.3 pin functions......................................................................................................... 137 8.2.4 pin states ............................................................................................................... 1 39 8.3 port 2 ...................................................................................................................... ............ 140 8.3.1 overview ............................................................................................................... 140 8.3.2 register configuration and description................................................................ 140 8.3.3 pin functions......................................................................................................... 144 8.3.4 pin states ............................................................................................................... 1 44 8.4 port 3 ...................................................................................................................... ............ 145 8.4.1 overview ............................................................................................................... 145 8.4.2 register configuration and description................................................................ 145 8.4.3 pin functions......................................................................................................... 149 8.4.4 pin states ............................................................................................................... 1 51 8.4.5 mos input pull-up ............................................................................................... 151 8.5 port 4 ...................................................................................................................... ............ 152 8.5.1 overview ............................................................................................................... 152 8.5.2 register configuration and description................................................................ 152 8.5.3 pin functions......................................................................................................... 154 8.5.4 pin states ............................................................................................................... 1 55 8.6 port 5 ...................................................................................................................... ............ 155 8.6.1 overview ............................................................................................................... 155 8.6.2 register configuration and description................................................................ 156 8.6.3 pin functions......................................................................................................... 158 8.6.4 pin states ............................................................................................................... 1 58 8.6.5 mos input pull-up ............................................................................................... 159 8.7 port 6 ...................................................................................................................... ............ 159 8.7.1 overview ............................................................................................................... 159 8.7.2 register configuration and description................................................................ 160 8.7.3 pin functions......................................................................................................... 161 8.7.4 pin states ............................................................................................................... 1 62 8.7.5 mos input pull-up ............................................................................................... 162 8.8 port 7 ...................................................................................................................... ............ 163 8.8.1 overview ............................................................................................................... 163 8.8.2 register configuration and description................................................................ 163 8.8.3 pin functions......................................................................................................... 164 8.8.4 pin states ............................................................................................................... 1 65 8.9 port 8 ...................................................................................................................... ............ 165 8.9.1 overview ............................................................................................................... 165 8.9.2 register configuration and description................................................................ 165 8.9.3 pin functions......................................................................................................... 167 v 8.9.4 pin states ............................................................................................................... 1 67 8.10 port 9 ..................................................................................................................... ............. 168 8.10.1 overview ............................................................................................................... 16 8 8.10.2 register configuration and description................................................................ 168 8.10.3 pin functions......................................................................................................... 169 8.10.4 pin states ............................................................................................................... 171 8.11 port a..................................................................................................................... ............. 171 8.11.1 overview ............................................................................................................... 17 1 8.11.2 register configuration and description................................................................ 172 8.11.3 pin functions......................................................................................................... 173 8.11.4 pin states ............................................................................................................... 174 8.12 port b..................................................................................................................... ............. 175 8.12.1 overview ............................................................................................................... 17 5 8.12.2 register configuration and description................................................................ 175 8.13 port c..................................................................................................................... ............. 176 8.13.1 overview ............................................................................................................... 17 6 8.13.2 register configuration and description................................................................ 176 section 9 timers ................................................................................................................. 177 9.1 overview .................................................................................................................... ........ 177 9.2 timer a ..................................................................................................................... ......... 178 9.2.1 overview ............................................................................................................... 178 9.2.2 register descriptions ............................................................................................ 180 9.2.3 timer operation .................................................................................................... 182 9.2.4 timer a operation states...................................................................................... 183 9.3 timer b ..................................................................................................................... ......... 183 9.3.1 overview ............................................................................................................... 183 9.3.2 register descriptions ............................................................................................ 185 9.3.3 timer operation .................................................................................................... 187 9.3.4 timer b operation states...................................................................................... 188 9.4 timer c ..................................................................................................................... ......... 188 9.4.1 overview ............................................................................................................... 188 9.4.2 register descriptions ............................................................................................ 190 9.4.3 timer operation .................................................................................................... 192 9.4.4 timer c operation states...................................................................................... 194 9.5 timer f ..................................................................................................................... .......... 194 9.5.1 overview ............................................................................................................... 194 9.5.2 register descriptions ............................................................................................ 197 9.5.3 interface with the cpu.......................................................................................... 203 9.5.4 timer operation .................................................................................................... 206 9.5.5 application notes.................................................................................................. 208 9.6 timer g ..................................................................................................................... ......... 210 9.6.1 overview ............................................................................................................... 210 vi 9.6.2 register descriptions ............................................................................................ 212 9.6.3 noise canceller circuit ......................................................................................... 215 9.6.4 timer operation .................................................................................................... 217 9.6.5 application notes.................................................................................................. 221 9.6.6 sample timer g application ................................................................................ 224 section 10 serial communication interface ................................................................. 225 10.1 overview .................................................................................................................. ......... 225 10.2 sci1...................................................................................................................... .............. 225 10.2.1 overview ............................................................................................................... 2 25 10.2.2 register descriptions ............................................................................................ 227 10.2.3 operation ............................................................................................................... 231 10.2.4 interrupts .............................................................................................................. . 234 10.2.5 application notes.................................................................................................. 234 10.3 sci2...................................................................................................................... .............. 234 10.3.1 overview ............................................................................................................... 2 34 10.3.2 register descriptions ............................................................................................ 236 10.3.3 operation ............................................................................................................... 240 10.3.4 interrupts .............................................................................................................. . 247 10.3.5 application notes.................................................................................................. 247 10.4 sci3...................................................................................................................... .............. 248 10.4.1 overview ............................................................................................................... 2 48 10.4.2 register descriptions ............................................................................................ 250 10.4.3 operation ............................................................................................................... 266 10.4.4 operation in asynchronous mode ........................................................................ 270 10.4.5 operation in synchronous mode .......................................................................... 278 10.4.6 multiprocessor communication function ............................................................ 285 10.4.7 interrupts .............................................................................................................. . 291 10.4.8 application notes.................................................................................................. 292 section 11 14-bit pwm ...................................................................................................... 297 11.1 overview .................................................................................................................. .......... 297 11.1.1 features ................................................................................................................ . 297 11.1.2 block diagram ...................................................................................................... 297 11.1.3 pin configuration .................................................................................................. 298 11.1.4 register configuration .......................................................................................... 298 11.2 register descriptions..................................................................................................... ..... 298 11.2.1 pwm control register (pwcr)........................................................................... 298 11.2.2 pwm data registers u and l (pwdru, pwdrl)............................................. 299 11.3 operation ................................................................................................................. ........... 299 section 12 a/d converter .................................................................................................. 301 12.1 overview .................................................................................................................. .......... 301 vii 12.1.1 features ................................................................................................................ . 301 12.1.2 block diagram ...................................................................................................... 301 12.1.3 pin configuration .................................................................................................. 302 12.1.4 register configuration.......................................................................................... 302 12.2 register descriptions..................................................................................................... ..... 303 12.2.1 a/d result register (adrr)................................................................................ 303 12.2.2 a/d mode register (amr) .................................................................................. 303 12.2.3 a/d start register (adsr)................................................................................... 305 12.3 operation ................................................................................................................. ........... 306 12.3.1 a/d conversion operation.................................................................................... 306 12.3.2 start of a/d conversion by external trigger input.............................................. 306 12.4 interrupts ................................................................................................................ ............ 307 12.5 typical use ............................................................................................................... ......... 307 12.6 application notes......................................................................................................... ...... 310 section 13 lcd controller/driver .................................................................................. 311 13.1 overview .................................................................................................................. .......... 311 13.1.1 features ................................................................................................................ . 311 13.1.2 block diagram ...................................................................................................... 312 13.1.3 pin configuration .................................................................................................. 313 13.1.4 register configuration .......................................................................................... 313 13.2 register descriptions..................................................................................................... ..... 314 13.2.1 lcd port control register (lpcr)...................................................................... 314 13.2.2 lcd control register (lcr)................................................................................ 316 13.3 operation ................................................................................................................. ........... 318 13.3.1 settings prior to lcd display .............................................................................. 318 13.3.2 relation of lcd ram to display ........................................................................ 320 13.3.3 connection to hd66100........................................................................................ 320 13.3.4 operation in power-down modes ........................................................................ 329 13.3.5 boosting the lcd driver power supply .............................................................. 330 section 14 electrical characteristics ............................................................................... 331 14.1 h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s and h8/3837s absolute maximum ratings (standard specifications) ..................................................... 331 14.2 h8/3832s, h8/3833s and h8/3834s electrical characteristics (standard specifications).................................................................................................... 33 2 14.2.1 power supply voltage and operating range........................................................ 332 14.2.2 dc characteristics ................................................................................................ 334 14.2.3 ac characteristics ................................................................................................ 339 14.2.4 a/d converter characteristics .............................................................................. 343 14.2.5 lcd characteristics .............................................................................................. 344 14.3 h8/3835s, h8/3836s and h8/3837s electrical characteristics (standard specifications).................................................................................................... 34 5 viii 14.3.1 power supply voltage and operating range........................................................ 345 14.3.2 dc characteristics ................................................................................................ 347 14.3.3 ac characteristics ................................................................................................ 352 14.3.4 a/d converter characteristics .............................................................................. 356 14.3.5 lcd characteristics .............................................................................................. 357 14.4 h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s and h8/3837s absolute maximum ratings (wide temperature range (i-spec) version)...................... 358 14.5 h8/3832s, h8/3833s and h8/3834s electrical characteristics (wide temperature range (i-spec) version) .................................................................... 359 14.5.1 power supply voltage and operating range........................................................ 359 14.5.2 dc characteristics ................................................................................................ 361 14.5.3 ac characteristics ................................................................................................ 366 14.5.4 a/d converter characteristics .............................................................................. 370 14.5.5 lcd characteristics .............................................................................................. 371 14.6 h8/3835s, h8/3836s and h8/3837s electrical characteristics (wide temperature range (i-spec) version) .................................................................... 373 14.6.1 power supply voltage and operating range........................................................ 373 14.6.2 dc characteristics ................................................................................................ 375 14.6.3 ac characteristics ................................................................................................ 380 14.6.4 a/d converter characteristics .............................................................................. 384 14.6.5 lcd characteristics .............................................................................................. 385 14.7 h8/3833, h8/3834, h8/3835, h8/3836, and h8/3837 (standard specification) absolute maximum ratings............................................................................................... 387 14.8 h8/3833 and h8/3834 electrical characteristics (standard specifications)...................... 388 14.8.1 power supply voltage and operating range........................................................388 14.8.2 dc characteristics ................................................................................................ 390 14.8.3 ac characteristics ................................................................................................ 395 14.8.4 a/d converter characteristics .............................................................................. 399 14.8.5 lcd characteristics .............................................................................................. 400 14.9 h8/3835 and h8/3836 and h8/3837 (standard specifications) electrical characteristics.................................................................................................... 4 01 14.9.1 power supply voltage and operating range........................................................ 401 14.9.2 dc characteristics ................................................................................................ 403 14.9.3 ac characteristics ................................................................................................ 408 14.9.4 a/d converter characteristics .............................................................................. 412 14.9.5 lcd characteristics .............................................................................................. 413 14.10 h8/3833, h8/3834, h8/3835, h8/3836, and h8/3837 absolute maximum ratings (wide temperature range (i-spec) version) .................................................................... 414 14.11 h8/3833 and h8/3834 electrical characteristics (wide temperature range (i-spec) version).............................................................................................................. .. 415 14.11.1 power supply voltage and operating range........................................................ 415 14.11.2 dc characteristics ................................................................................................ 417 14.11.3 ac characteristics ................................................................................................ 422 ix 14.11.4 a/d converter characteristics .............................................................................. 426 14.11.5 lcd characteristics .............................................................................................. 427 14.12 h8/3835, h8/3836, and h8/3837 electrical characteristics (wide temperature range (i-spec) version) .................................................................... 429 14.12.1 power supply voltage and operating range........................................................ 429 14.12.2 dc characteristics ................................................................................................ 431 14.12.3 ac characteristics ................................................................................................ 436 14.12.4 a/d converter characteristics .............................................................................. 440 14.12.5 lcd characteristics .............................................................................................. 441 14.13 operation timing .......................................................................................................... ..... 443 14.14 output load circuit....................................................................................................... ..... 448 appendix a cpu instruction set ..................................................................................... 449 a.1 instructions ............................................................................................................... .......... 449 a.2 operation code map ......................................................................................................... . 457 a.3 number of execution states............................................................................................... 45 9 appendix b on-chip registers ........................................................................................ 466 b.1 i/o registers (1) .......................................................................................................... ....... 466 b.2 i/o registers (2) .......................................................................................................... ....... 470 appendix c i/o port block diagrams ............................................................................ 513 c.1 block diagram of port 1 .................................................................................................... 513 c.2 block diagram of port 2 .................................................................................................... 518 c.3 block diagram of port 3 .................................................................................................... 521 c.4 block diagram of port 4 .................................................................................................... 527 c.5 block diagram of port 5 .................................................................................................... 530 c.6 block diagram of port 6 .................................................................................................... 531 c.7 block diagram of port 7 .................................................................................................... 532 c.8 block diagram of port 8 .................................................................................................... 533 c.9 block diagram of port 9 .................................................................................................... 534 c.10 block diagram of port a................................................................................................... . 535 c.11 block diagram of port b................................................................................................... . 536 c.12 block diagram of port c................................................................................................... . 536 appendix d port states in the different processing states ....................................... 537 appendix e list of products codes ................................................................................. 538 appendix f package dimensions ..................................................................................... 542 1 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3834 series features an on-chip liquid crystal display (lcd) controller/driver. other on-chip peripheral functions include five timers, a 14-bit pulse width modulator (pwm), three serial communication interface channels, and an analog-to-digital (a/d) converter. together these functions make the h8/3834 series ideally suited for embedded control of systems requiring an lcd display. on-chip memory is 16 kbytes of rom and 1 kbyte of ram in the h8/3832s, 24 kbytes of rom and 1 kbyte of ram in the h8/3833(s), 32 kbytes of rom and 1 kbyte of ram in the h8/3834(s), 40 kbytes of rom and 2 kbytes of ram in the h8/3835(s), 48 kbytes of rom and 2 kbytes of ram in the h8/3836(s), and 60 kbytes of rom and 2 kbytes of ram in the h8/3837(s). the h8/3834 and h8/3837 both include a ztat? version*, featuring a user-programmable on- chip prom. table 1.1 summarizes the features of the h8/3834 series. note: * ztat is a trademark of hitachi, ltd. table 1.1 features item description cpu high-speed h8/300l cpu general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) operating speed ? max. operating speed: 5 mhz ? add/subtract: 0.4 s (operating at 5 mhz) ? multiply/divide: 2.8 s (operating at 5 mhz) ? can run on 32.768 khz subclock instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers 2 table 1.1 features (cont) item description cpu typical instructions multiply (8 bits 8 bits) divide (16 bits ? 8 bits) bit accumulator register-indirect designation of bit position interrupts 33 interrupt sources 13 external interrupt pins: irq 4 to irq 0 , wkp 7 to wkp 0 20 internal interrupt sources clock pulse generators two on-chip clock pulse generators system clock pulse generator: 1 to 10 mhz subclock pulse generator: 32.768 khz power-down modes six power-down modes sleep mode standby mode watch mode subsleep mode subactive mode active (medium-speed) mode memory large on-chip memory h8/3832s: 16-kbyte rom, 1-kbyte ram h8/3833(s): 24-kbyte rom, 1-kbyte ram h8/3834(s): 32-kbyte rom, 1-kbyte ram h8/3835(s): 40-kbyte rom, 2-kbyte ram h8/3836(s): 48-kbyte rom, 2-kbyte ram h8/3837(s): 60-kbyte rom, 2-kbyte ram i/o ports 84 i/o port pins i/o pins: 71 input pins: 13 timers five on-chip timers timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock ( f ) * and four clock signals divided from the watch clock ( f w ) * note: * f and f w are defined in section 4, clock pulse generators. 3 table 1.1 features (cont) item description timers timer b: 8-bit timer ? count-up timer with selection of seven internal clock signals or event input from external pin ? auto-reloading timer c: 8-bit timer ? count-up/count-down timer with selection of seven internal clock signals or event input from external pin ? auto-reloading timer f: 16-bit timer ? can be used as two independent 8-bit timers. ? count-up timer with selection of four internal clock signals or event input from external pin ? compare-match function with toggle output timer g: 8-bit timer ? count-up timer with selection of four internal clock signals ? input capture function with built-in noise canceller circuit serial communication interface three channels on chip sci1: synchronous serial interface choice of 8-bit or 16-bit data transfer sci2: 8-bit synchronous serial interface automatic transfer of 32-byte data segments sci3: 8-bit synchronous or asynchronous serial interface built-in function for multiprocessor communication 14-bit pwm pulse-division pwm output for reduced ripple can be used as a 14-bit d/a converter by connecting to an external low-pass filter. a/d converter successive approximations using a resistance ladder resolution: 8 bits 12-channel analog input port conversion time: 31/ f or 62/ f per channel lcd controller/driver up to 40 segment pins and 4 common pins choice of four duty cycles (static, 1/2, 1/3, 1/4) segments can be expanded externally segment pins can be switched to general-purpose ports in groups of four 4 table 1.1 features (cont) item description product lineup product code mask rom version ztat version package rom/ram size hd6433832sh hd6433832sf hd6433832sx hd6433833h hd6433833sh hd6433833f hd6433833sf hd6433833x hd6433833sx hd6433834h hd6433834sh hd6433834f hd6433834sf hd6433834x hd6433834sx hd6433835h hd6433835sh hd6433835f hd6433835sf hd6433835x hd6433835sx hd6433836h hd6433836sh hd6433836f hd6433836sf hd6433836x hd6433836sx hd6433837h hd6433837sh hd6433837f hd6433837sf hd6433837x hd6433837sx hd6433832sd hd6433832se hd6433832sl hd6433833d hd6433833sd hd6433833e hd6433833se hd6433833l hd6433833sl hd6433834d hd6433834sd hd6433834e hd6433834se hd6433834l hd6433834sl hd6433835d hd6433835sd hd6433835e hd6433835se hd6433835l hd6433835sl hd6433836d hd6433836sd hd6433836e hd6433836se hd6433836l hd6433836sl hd6433837d hd6433837sd hd6433837e hd6433837se hd6433837l hd6433837sl hd6473834h hd6473834f hd6473834x HD6473837H hd6473837f hd6473837x hd6473834d hd6473834e hd6473837d hd6473837e hd6473837l 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) 100-pin qfp (fp-100b) 100-pin qfp (fp-100a) 100-pin tqfp (tfp-100b) rom: 16 kbytes ram: 1 kbyte rom: 24 kbytes ram: 1 kbyte rom: 32 kbytes ram: 1 kbyte rom: 40 kbytes ram: 2 kbytes rom: 48 kbytes ram: 2 kbytes rom: 60 kbytes ram: 2 kbytes rom: 16 kbytes ram: 1 kbyte wtr (i-spec) rom: 24 kbytes ram: 1 kbyte wtr (i-spec) rom: 32 kbytes ram: 1 kbyte wtr (i-spec) rom: 40 kbytes ram: 2 kbytes wtr (i-spec) rom: 48 kbytes ram: 2 kbytes wtr (i-spec) rom: 60 kbytes ram: 2 kbytes wtr (i-spec) 5 1.2 internal block diagram figure 1.1 shows a block diagram of the h8/3834 series. pc 0 /an 8 pc 1 /an 9 pc 2 /an 10 pc 3 /an 11 v ss v ss v cc v cc osc 1 osc 2 x 1 x 2 res test mdo p9 7 /seg 40 /cl 1 p9 6 /seg 39 /cl 2 p9 5 /seg 38 /do p9 4 /seg 37 /m p9 3 /seg 36 p9 2 /seg 35 p9 1 /seg 34 p9 0 /seg 33 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 /pwm p1 5 / irq 1 /tmib p1 6 / irq 2 /tmic p1 7 / irq 3 /tmif p2 0 / irq 4 / adtrg p2 1 /ud p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 / cs p4 0 /sck 3 p4 1 /rxd p4 2 /txd p4 3 / irq 0 p5 0 / wkp 0 /seg 1 p5 1 / wkp 1 /seg 2 p5 2 / wkp 2 /seg 3 p5 3 / wkp 3 /seg 4 p5 4 / wkp 4 /seg 5 p5 5 / wkp 5 /seg 6 p5 6 / wkp 6 /seg 7 p5 7 / wkp 7 /seg 8 v 1 v 2 v 3 av cc av ss pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 cpu h8/300l data bus (lower) rom ram timer a timer b sci1 timer c sci2 timer f sci3 timer g 14-bit pwm a/d converter lcd controller port 6 port 7 port 8 port 9 port a lcd driver power supply system clock oscillator port b port c address bus data bus (upper) subclock oscillator port 1 port 2 port 3 port 4 port 5 figure 1.1 block diagram 6 1.3 pin arrangement and functions 1.3.1 pin arrangement the pin arrangement of the h8/3834 series is shown in figures 1.2 and 1.3. p9 7 /seg 40 /cl 1 p9 6 /seg 39 /cl 2 p9 5 /seg 38 /do p9 4 /seg 37 /m p9 3 /seg 36 p9 2 /seg 35 p9 1 /seg 34 p9 0 /seg 33 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 pc 2 /an 10 pc 1 /an 9 pc 0 /an 8 pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 av cc p4 3 / irq 0 p4 2 /txd p4 1 /rxd p4 0 /sck 3 p1 7 / irq 3 /tmif p1 6 / irq 2 /tmic p1 5 / irq 1 /tmib p1 4 /pwm p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow v cc pc 3 /an 11 av ss test x 2 x 1 v ss osc 1 osc 2 res mdo p2 0 / irq 4 / adtrg p2 1 /ud p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 / cs v ss v 3 v 2 v 1 v cc pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p5 0 / wkp 0 /seg 1 p5 1 / wkp 1 /seg 2 p5 2 / wkp 2 /seg 3 p5 3 / wkp 3 /seg 4 p5 4 / wkp 4 /seg 5 p5 5 / wkp 5 /seg 6 p5 6 / wkp 6 /seg 7 p5 7 / wkp 7 /seg 8 p6 0 /seg 9 p6 1 /seg 10 p6 2 /seg 11 p6 3 /seg 12 p6 4 /seg 13 p6 5 /seg 14 p6 6 /seg 15 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 figure 1.2 pin arrangement (fp-100b, tfp-100b: top view) 7 pc 0 /an 8 pc 1 /an 9 pc 2 /an 10 pc 3 /an 11 av ss test x 2 x 1 v ss osc 1 osc 2 res mdo p2 0 / irq 4 / adtrg p2 1 /ud p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 / cs v ss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 58 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p1 0 /tmow v cc p9 7 /seg 40 /cl 1 p9 6 /seg 39 /cl 2 p9 5 /seg 38 /do p9 4 /seg 37 /m p9 3 /seg 36 p9 2 /seg 35 p9 1 /seg 34 p9 0 /seg 33 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 av cc p4 3 / irq 0 p4 2 /txd p4 1 /rxd p4 0 /sck 3 p1 7 / irq 3 /tmif p1 6 / irq 2 /tmic p1 5 / irq 1 /tmib p1 4 /pwm p1 3 /tmig p1 2 /tmofh p1 1 /tmofl v 3 v 2 v 1 v cc pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p5 0 / wkp 0 /seg 1 p5 1 / wkp 1 /seg 2 p5 2 / wkp 2 /seg 3 p5 3 / wkp 3 /seg 4 p5 4 / wkp 4 /seg 5 p5 5 / wkp 5 /seg 6 p5 6 / wkp 6 /seg 7 p5 7 / wkp 7 /seg 8 p6 0 /seg 9 p6 1 /seg 10 p6 2 /seg 11 p6 3 /seg 12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 figure 1.3 pin arrangement (fp-100a: top view) 8 1.3.2 pin functions table 1.2 outlines the pin functions of the h8/3834 series. table 1.2 pin functions pin no. type symbol fp-100b tfp-100b fp-100a i/o name and functions power source pins v cc 31, 76 34, 79 input power supply: all v cc pins should be connected to the system power supply (+5 v) v ss 6, 27 9, 30 input ground: all v ss pins should be connected to the system power supply (0 v) av cc 89 92 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5 v). av ss 2 5 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0 v). v 1 , v 2 , v 3 30, 29, 28 33, 32, 31 input lcd power supply: these are power supply pins for the lcd controller/ driver. a built-in resistor divider is provided for the power supply, so these pins are normally left open. power supply conditions are v cc 3 v 1 3 v 2 3 v 3 3 v ss . clock pins osc 1 7 10 input this pin connects to a crystal or ceramic oscillator, or can be used to input an external clock. osc 2 8 11 output see section 4, clock pulse generators, for a typical connection diagram. x 1 5 8 input this pin connects to a 32.768-khz crystal oscillator. x 2 4 7 output see section 4, clock pulse generators, for a typical connection diagram. 9 table 1.2 pin functions (cont) pin no. type symbol fp-100b tfp-100b fp-100a i/o name and functions system control res 9 12 input reset: when this pin is driven low, the chip is reset mdo 10 13 input mode: this pin controls system clock oscillation in the reset state test 3 6 input test: this is a test pin, not for use in application systems. it should be connected to v ss . interrupt pins irq 0 irq 1 irq 2 irq 3 irq 4 88 82 83 84 11 91 85 86 87 14 input external interrupt request 0 to 4: these are input pins for external interrupts for which there is a choice between rising and falling edge sensing wkp 7 to wkp 0 43 to 36 46 to 39 input wakeup interrupt request 0 to 7: these are input pins for external interrupts that are detected at the falling edge timer pins tmow 77 80 output clock output: this is an output pin for waveforms generated by the timer a output circuit tmib 82 85 input timer b event counter input: this is an event input pin for input to the timer b counter tmic 83 86 input timer c event counter input: this is an event input pin for input to the timer c counter ud 12 15 input timer c up/down select: this pin selects whether the timer c counter isused for up- or down-counting. at high level it selects up-counting, and at low level down-counting. tmif 84 87 input timer f event counter input: this is an event input pin for input to the timer f counter tmofl 78 81 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function 10 table 1.2 pin functions (cont) pin no. type symbol fp-100b tfp-100b fp-100a i/o name and functions timer pins tmofh 79 82 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function tmig 80 83 input timer g capture input: this is an input pin for the timer g input capture function 14-bit pwm pin pwm 81 84 output 14-bit pwm output: this is an output pin for waveforms generated by the 14-bit pwm i/o ports pb 7 to pb 0 97 to 90 100 to 93 input port b: this is an 8-bit input port pc 3 to pc 0 1, 100 to 98 4 to 1 input port c: this is a 4-bit input port p4 3 88 91 input port 4 (bit 3): this is a 1-bit input port p4 2 to p4 0 87 to 85 90 to 88 i/o port 4 (bits 2 to 0): this is a 3-bit i/o port. input or output can be designated for each bit by means of port control register 4 (pcr4). pa 3 to pa 0 32 to 35 35 to 38 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). p1 7 to p1 0 84 to 77 87 to 80 i/o port 1: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 1 (pcr1). p2 7 to p2 0 18 to 11 21 to 14 i/o port 2: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 2 (pcr2). p3 7 to p3 0 26 to 19 29 to 22 i/o port 3: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 3 (pcr3). p5 7 to p5 0 43 to 36 46 to 39 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5). 11 table 1.2 pin functions (cont) pin no. type symbol fp-100b tfp-100b fp-100a i/o name and functions i/o ports p6 7 to p6 0 51 to 44 54 to 47 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 59 to 52 62 to 55 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 67 to 60 70 to 63 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). p9 7 to p9 0 75 to 68 78 to 71 i/o port 9: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 9 (pcr9). serial com- munication interface (sci) si 1 so 1 20 21 23 24 input output sci1 receive data input: this is the sci1 data input pin sci1 send data output: this is the sci1 data output pin sck 1 19 22 i/o sci1 clock i/o : this is the sci1 clock i/o pin si 2 23 26 input sci2 receive data input: this is the sci2 data input pin so 2 24 27 output sci2 send data output: this is the sci2 data output pin sck 2 22 25 i/o sci2 clock i/o : this is the sci2 clock i/o pin cs 26 29 input sci2 chip select input: this pin controls the start of sci2 transfers strb 25 28 output sci2 strobe output: this pin outputs a strobe pulse each time a byte of data is transferred rxd 86 89 input sci3 receive data input: this is the sci3 data input pin 12 table 1.2 pin functions (cont) pin no. type symbol fp-100b tfp-100b fp-100a i/o name and functions serial com- munication interface (sci) txd sck 3 87 85 90 88 output i/o sci3 send data output: this is the sci3 data output pin sci3 clock i/o : this is the sci3 clock i/o pin a/d converter an 11 to an 0 1, 100 to 90 4 to 1 100 to 93 input analog input channels 0 to 11: these are analog data input channels to the a/d converter adtrg 11 14 input a/d converter trigger input: this is the external trigger input pin to the a/d converter lcd controller/ driver com 4 to com 1 32 to 35 35 to 38 output lcd common output: these are lcd common output pins seg 40 to seg 1 75 to 36 78 to 39 output lcd segment output: these are lcd segment output pins cl 1 75 78 output lcd latch clock: this is the display data latch clock output pin for external segment expansion cl 2 74 77 output lcd shift clock: this is the display data shift clock output pin for external segment expansion do 73 76 output lcd serial data output: this is the serial display data output pin for external segment expansion m 72 75 output lcd alternating signal output: this is the lcd alternating signal output pin for external segment expansion 13 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise, optimized instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect 64-kbyte address space high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 8-bit multiply: 2.8 s* 16 8-bit divide: 2.8 s* note: * these values are at f = 5 mhz. low-power operation modes sleep instruction for transfer to low-power operation 14 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers 15 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. 16 bit 7interrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6user bit (u): can be used freely by the user. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4user bit (u): can be used freely by the user. bit 3negative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2zero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0carry flag (c): set to 1 when operation execution generates a carry, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 17 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. to prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). all arithmetic and logic instructions except adds and subs can operate on byte data. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. 18 2.3.1 data formats in general registers the general register data formats are shown in figure 2.3. 76543210 don? care data type register no. data format 70 1-bit data rnh 76543210 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 figure 2.3 register data formats 19 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. for access by the h8/300l cpu, word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, the access is performed at the preceding even address. this rule affects the mov.w instruction, and also applies to instruction fetching. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. for the ccr, the same value is stored in the upper 8 bits and lower 8 bits as word data. on return, the lower 8 bits are ignored. 20 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @Crn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register directrn: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect@rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement@(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. 21 4. register indirect with post-increment or pre-decrement@rn+ or @Crn: register indirect with post-increment@rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement@Crn the @Crn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address@aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate#xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative@(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is C126 to +128 bytes (C63 to +64 words) from the current address. the displacement should be an even number. 22 8. memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (8- bit) (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to specify the bit position. 23 table 2.2 effective address calculation no. addressing mode and instruction format effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn op rm rn 87 3 40 15 rm 30 rn 30 2 op rm 76 3 40 15 register indirect, @rn contents (16 bits) of register indicated by rm 0 15 0 15 3 register indirect with displacement, @(d:16, rn) op rm 76 3 40 15 disp 0 15 disp 0 15 contents (16 bits) of register indicated by rm 4 op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @?n incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 1 or 2 0 15 0 15 1 or 2 0 15 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm 24 table 2.2 effective address calculation (cont) no. addressing mode and instruction format effective address calculation method effective address (ea) 5 absolute address @aa:8 @aa:16 op 87 0 15 0 15 abs h'ff 87 0 15 0 15 abs op 6 op 0 15 imm #xx:16 op 87 0 15 imm immediate #xx:8 operand is 1- or 2-byte immediate data 7 op disp 70 15 program-counter relative @(d:8, pc) pc contents 0 15 0 15 8 sign extension disp 25 table 2.2 effective address calculation (cont) no. addressing mode and instruction format effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 abs notation: rm, rn: register field op: operation field disp: displacement imm: immediate data abs: absolute address 26 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @Csp. pop rn is equivalent to mov.w @sp+, rn. the machine language is also the same. 2. bcc is the generic term for conditional branch instructions. the functions of the instructions are shown in tables 2.4 to 2.11. the meaning of the operation symbols used in the tables is as follows. 27 notation rd general register (destination) rs general register (source) rn general register (ead), 28 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @Crn, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @Cr7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. push w rn ? @Csp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @Csp. note: * size: operand size b: byte w: word certain precautions are required in data access. see 2.9.1, notes on data access, for details. 29 15 0 87 op rm rn mov rm ? rn 15 0 87 op rm rn @rm ?? rn 15 0 87 op rm rn @(d:16, rm) ?? rn disp 15 0 87 op rm rn @rm+ ? rn, or rn ? @?m 15 0 87 op rn abs @aa:8 ?? rn 15 0 87 op rn @aa:16 ?? rn abs 15 0 87 op rn imm #xx:8 ? rn 15 0 87 op rn #xx:16 ? rn imm 15 0 87 op rn push, pop notation: op: rm, rn: disp: abs: imm: operation field register field displacement absolute address immediate data @sp+ rn, or rn @?p ? ? 111 figure 2.5 data transfer instruction codes 30 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs ? rd, rd + #imm ? rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc dec b rd 1 ? rd increments or decrements a general register adds subs w rd 1 ? rd, rd 2 ? rd adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. daa das b rd decimal adjust ? rd decimal-adjusts (adjusts to packed 4-bit bcd) an addition or subtraction result in a general register by referring to the ccr mulxu b rd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result divxu b rd rs ? rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and the result is stored in the ccr. word data can be compared only between two general registers. neg b 0 C rd ? rd obtains the twos complement (arithmetic complement) of data in a general register note: * size: operand size b: byte w: word 31 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data or b rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data xor b rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data not b ~ rd ? rd obtains the ones complement (logical complement) of general register contents note: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift ? rd performs an arithmetic shift operation on general register contents shll shlr b rd shift ? rd performs a logical shift operation on general register contents rotl rotr b rd rotate ? rd rotates general register contents rotxl rotxr b rd rotate through carry ? rd rotates general register contents through the c (carry) bit notes: * size: operand size b: byte 32 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes 33 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 ? ( 34 table 2.8 bit-manipulation instructions (cont) instruction size * function bxor b c ? ( 35 15 0 87 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes 36 notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont) 37 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches to the designated address if the specified condition is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine 38 notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes 39 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register stc b ccr ? rd copies the condition code register to a specified general register andc b ccr #imm ? ccr logically ands the condition code register with immediate data orc b ccr #imm ? ccr logically ors the condition code register with immediate data xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data nop pc + 2 ? pc only increments the program counter note: * size: operand size b: byte notation: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 40 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 1 0 then repeat @r5+ ? @r6+ r4l C 1 ? r4l until r4l = 0 else next; block transfer instruction. transfers the number of bytes specified by r4l, from locations starting at the address specified by r5, to locations starting at the address specified by r6. on completion of the transfer, the next instruction is executed. certain precautions are required in using the eepmov instruction. see 2.9.3, notes on use of the eepmov instruction, for details. notation: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code 41 2.6 basic operational timing cpu operation is synchronized by a system clock ( f ) or a subclock ( f sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of f or f sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or ff figure 2.11 on-chip memory access cycle 42 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2.12 and 2.13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub or ff figure 2.12 on-chip peripheral module access cycle (2-state access) 43 three-state access to on-chip peripheral modules t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or ff figure 2.13 on-chip peripheral module access cycle (3-state access) 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. 44 cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state entered when the cpu changes the processing flow due to a reset or interrupt exception handling source. the cpu is initialized. note: see section 5, power-down modes, for details on the modes and their transitions. figure 2.14 cpu operation states 45 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs exception- handling request exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3, exception handling. 46 2.8 memory map 2.8.1 memory map figure 2.16 shows the h8/3832 memory map. figure 2.17 shows the h8/3833 memory map. figure 2.18 shows the h8/3834 memory map. figure 2.19 shows the h8/3835 memory map. figure 2.20 shows the h8/3836 memory map. figure 2.21 shows the h8/3837 memory map. interrupt vector area on-chip rom on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) lcd ram (64 bytes) reserved reserved * note: the lcd ram addresses are the addresses after a reset. 16 kbytes (16,384 bytes) 1,024 bytes h'0000 h'0029 h'002a h'3fff h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff * figure 2.16 h8/3832 memory map 47 interrupt vector area on-chip rom on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) lcd ram (64 bytes) reserved reserved * note: the lcd ram addresses are the addresses after a reset. 24 kbytes (24,576 bytes) 1,024 bytes h'0000 h'0029 h'002a h'5fff h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff * figure 2.17 h8/3833 memory map 48 interrupt vector area on-chip rom on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) lcd ram (64 bytes) reserved reserved * note: the lcd ram addresses are the addresses after a reset. 32 kbytes (32,768 bytes) 1,024 bytes h'0000 h'0029 h'002a h'7fff h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff * figure 2.18 h8/3834 memory map 49 h'0000 h'0029 h'002a h'9fff h'f77f h'f780 h'f740 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff interrupt vector area on-chip rom reserved lcd ram (64 bytes) on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) * 40 kbytes (40,960 bytes) 2,048 bytes note: the lcd ram addresses are the addresses after a reset. * figure 2.19 h8/3835 memory map 50 h'0000 h'0029 h'002a h'bfff h'f77f h'f780 h'f740 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff interrupt vector area on-chip rom reserved lcd ram (64 bytes) on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) * 48 kbytes (49,152 bytes) 2,048 bytes note: the lcd ram addresses are the addresses after a reset. * figure 2.20 h8/3836 memory map 51 h'0000 h'0029 h'002a h'edff h'f740 h'f77f h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff interrupt vector area on-chip rom reserved lcd ram (64 bytes) on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) note: the lcd ram addresses are the addresses after a reset. * * 60 kbytes (60,928 bytes) 2,048 bytes h'f780 figure 2.21 h8/3837 memory map 52 2.8.2 lcd ram address relocation after a reset, the lcd ram area is located at addresses h'f740 to h'f77f. however, this area can be relocated by setting the lcd ram relocation register (rlctr) bits. the lcd ram relocation register is explained below. lcd ram relocation register (rlctr: h'ffcf) bit 76543210 rlct1 rlct0 initial value 11111100 read/write r/wr/w rlctr is an 8-bit read/write register that selects the lcd ram address space. upon reset, rlctr is initialized to h'00. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. bits 1 and 0: lcd ram relocation select (rlct1, rlct0) bits 1 and 0 select the lcd ram address space. bit 1: rlct1 bit 0: rlct0 description 0 0 h'f740 toh'f77f (initial value) 1 h'f940 to h'f97f * 2 1 0 h'fb40 to h'fb7f * 2 1 h'fd40 to h'fd7f * 1, 2 notes: 1. in devices with 1,024-byte ram, if rlct1 to 0 are set to 11, on-chip ram addresses h'fb80 to h'fd7f become inaccessible. 2. in devices with 2,048-byte ram, if rlct1 to 0 are set to any value except 00, these on- chip ram addresses become inaccessible. 53 2.9 application notes 2.9.1 notes on data access access to empty areas: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu unpredictable data is transferred. access to internal i/o registers: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.22 shows the data size and number of states in which on-chip peripheral modules can be accessed. 54 interrupt vector area (42 bytes) on-chip rom on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) lcd ram (64 bytes) reserved 32 kbytes 1,024 bytes h'0000 h'0029 h'002a h'7fff h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff h'ffa8 h'ffad word byte access states 2 3 2 2 2 2 2 reserved notes: the above example is a description of the h8/3834. 1. the indicated addresses for the lcd ram area are initial values after system reset. 2. the h8/3832 has 16 kbytes of on-chip rom, and its ending address is h'3fff. the h8/3833 has 24 kbytes of on-chip rom, and its ending address is h'5fff. the h8/3835 has 40 kbytes of on-chip rom, and its ending address is h'9fff. the h8/3836 has 48 kbytes of on-chip rom, and its ending address is h'bfff. the h8/3837 has 60 kbytes of on-chip rom, and its ending address is h'edff. 3. the h8/3832 and h8/3833 have 1,024 bytes of on-chip ram and its starting address is h8/3834. the h8/3835, h8/3836, and h8/3837 each have 2,048 bytes of on-chip ram, and their starting address is h'f780. * 2 * 2 * 3 * 1 * 3 figure 2.22 data size and number of states for access to and from on-chip peripheral modules 55 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address bit manipulation in two registers assigned to the aame address example 1: timer load register and timer count bit manipulation figure 2.23 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. r w r: w: read write count clock timer counter timer load register reload internal bus figure 2.23 timer configuration example 56 example 2: when a bset instruction is executed on port 3 here a bset instruction is executed designating port 3. p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 0 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 00111111 pdr3 10000000 [b: bset instruction executed] bset #0 , @pdr3 the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 00111111 pdr3 01000001 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 0 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr3 data to h'41. finally, the cpu writes this value (h'41) to pdr3, completing execution of bset. 57 as a result of this operation, bit 0 in pdr3 becomes 1, and p3 0 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3. [a: prior to executing bset] mov. b #80, r0l mov. b r0l, @ram0 mov. b r0l, @pdr3 the pdr3 value (h'80) is written to a work area in memory (ram0) as well as to pdr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 00111111 pdr3 10000000 ram0 10000000 [b: bset instruction executed] bset #0 , @ram0 the bset instruction is executed designating the pdr3 work area (ram0). [c: after executing bset] mov. b @ram0, r0l mov. b r0l, @pdr3 the work area (ram0) value is written to pdr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 00111111 pdr3 10000001 ram0 10000001 58 bit manipulation in a register containing a write-only bit example 3: when a bclr instruction is executed on pcr3 of port 3 in this example, the port 3 control register pcr3 is accessed by a bclr instruction. as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 00111111 pdr3 10000000 [b: bclr instruction executed] bclr #0 , @pcr3 the bclr instruction is executed designating pcr3. [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr3 11111110 pdr3 10000000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr3 and bclr instruction execution ends. 59 as a result of this operation, bit 0 in pcr3 becomes 0, making p3 0 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3. [a: prior to executing bclr] mov. b #3f, r0l mov. b r0l, @ram0 mov. b r0l, @pcr3 the pcr3 value (h'3f) is written to a work area in memory (ram0) as well as to pcr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr3 00111111 pdr3 10000000 ram0 00111111 [b: bclr instruction executed] bclr #0 , @ram0 the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l mov. b r0l, @pcr3 the work area (ram0) value is written to pcr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr3 00111110 pdr3 10000000 ram0 00111110 table 2.12 lists registers that share the same address, and table 2.13 lists registers that contain write-only bits. 60 table 2.12 registers with shared addresses register name abbreviation address timer counter b and timer load register b tcb/tlb h'ffb3 timer counter c and timer load register c tcc/tlc h'ffb5 port data register 1 * pdr1 h'ffd4 port data register 2 * pdr2 h'ffd5 port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register 9 * pdr9 h'ffdc port data register a * pdra h'ffdd note: * these port registers are used also for pin input. table 2.13 registers with write-only bits register name abbreviation address port control register 1 pcr1 h'ffe4 port control register 2 pcr2 h'ffe5 port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register 9 pcr9 h'ffec port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm control register pwcr h'ffd0 pwm data register u pwdru h'ffd1 pwm data register l pwdrl h'ffd2 61 2.9.3 notes on use of the eepmov instruction the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. ? r6 ? r6 + r4l r5 ? r5 + r4l ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed ? r6 ? r6 + r4l r5 ? r5 + r4l ? 62 63 section 3 exception handling 3.1 overview exception handling is performed in the h8/3834 series when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the h8/3834 enters the reset state. to make sure the chip is reset properly, observe the following precautions. at power on: hold the res pin low until the clock pulse generator output stabilizes. resetting during operation: hold the res pin low for at least 10 system clock cycles. if the md0 pin is at the high level, reset exception handling begins when the res pin is held low for a given period, then returned to the high level. if the md0 pin is low, however, when the res pin is held low for a given period and then returned to high level, the reset is not cleared immediately. first the md0 pin must go from low to high, then after 8,192 clock cycles the reset is cleared and reset exception handling begins. 64 reset exception handling takes place as follows. the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc. when system power is turned on or off, the res pin should be held low. figures 3.1 and 3.2 show the reset sequence. vector fetch f internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) reset cleared md0 high (1) figure 3.1 reset sequence (when md0 pin is high) 65 vector fetch f internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) reset cleared md0 (1) 8,192 clock cycles figure 3.2 reset sequence (when md0 pin is low) 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). 66 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (wkp 0 to wkp 7 , irq 0 to irq 4 ), and 20 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: both internal and external interrupts can be masked by the i bit of ccr. when this bit is set to 1, interrupt request flags are set but interrupts are not accepted. the external interrupt pins irq 0 to irq 4 can each be set independently to either rising edge sensing or falling edge sensing. table 3.2 interrupt sources and priorities priority interrupt source interrupt vector number vector address high res reset 0 h'0000 to h'0001 irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irq 2 irq 2 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f irq 4 irq 4 8 h'0010 to h'0011 wkp 0 wkp 0 9 h'0012 to h'0013 wkp 1 wkp 1 wkp 2 wkp 2 wkp 3 wkp 3 wkp 4 wkp 4 wkp 5 wkp 5 wk p 6 wkp 6 wkp 7 wkp 7 sci1 sci1 transfer complete 10 h'0014 to h'0015 timer a timer a overflow 11 h'0016 to h'0017 timer b timer b overflow 12 h'0018 to h'0019 low timer c timer c overflow or underflow 13 h'001a to h'001b 67 table 3.2 interrupt sources and priorities (cont) priority interrupt source interrupt vector number vector address high timer fl timer fl compare match 14 h'001c to h'001d timer fl overflow timer fh timer fh compare match 15 h'001e to h'001f timer fh overflow timer g timer g input capture 16 h'0020 to h'0021 timer g overflow sci2 sci2 transfer complete 17 h'0022 to h'0023 sci2 transfer abort sci3 sci3 transmit end 18 h'0024 to h'0025 sci3 transmit data empty sci3 receive data full sci3 overrun error sci3 framing error sci3 parity error a/d converter a/d conversion end 19 h'0026 to h'0027 low (sleep instruction executed) direct transfer 20 h'0028 to h'0029 note: vector addresses h'0002 to h'0007 are reserved and cannot be used. 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers register name abbreviation r/w initial value address irq edge select register iegr r/w h'e0 h'fff2 interrupt enable register 1 ienr1 r/w h'00 h'fff3 interrupt enable register 2 ienr2 r/w h'00 h'fff4 interrupt request register 1 irr1 r/w * h'20 h'fff6 interrupt request register 2 irr2 r/w * h'00 h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 note: * write is enabled only for writing of 0 to clear a flag. 68 irq edge select register (iegr) bit 76543210 ieg4 ieg3 ieg2 ieg1 ieg0 initial value 11100000 read/write r/w r/w r/w r/w r/w iegr is an 8-bit read/write register, used to designate whether pins irq 0 to irq 4 are set to rising edge sensing or falling edge sensing. bits 7 to 5reserved bits: bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. bit 4irq 4 edge select (ieg4): bit 4 selects the input sensing of pin irq 4 / adtrg . bit 4: ieg4 description 0 falling edge of irq 4 / adtrg pin input is detected (initial value) 1 rising edge of irq 4 / adtrg pin input is detected bit 3irq 3 edge select (ieg3): bit 3 selects the input sensing of pin irq 3 /tmif. bit 3: ieg3 description 0 falling edge of irq 3 /tmif pin input is detected (initial value) 1 rising edge of irq 3 /tmif pin input is detected bit 2irq 2 edge select (ieg2): bit 2 selects the input sensing of pin irq 2 /tmic. bit 2: ieg2 description 0 falling edge of irq 2 /tmic pin input is detected (initial value) 1 rising edge of irq 2 /tmic pin input is detected bit 1irq 1 edge select (ieg1): bit 1 selects the input sensing of pin irq 1 /tmib. bit 1: ieg1 description 0 falling edge of irq 1 /tmib pin input is detected (initial value) 1 rising edge of irq 1 /tmib pin input is detected 69 bit 0irq 0 edge select (ieg0): bit 0 selects the input sensing of pin irq 0 . bit 0: ieg0 description 0 falling edge of irq 0 pin input is detected (initial value) 1 rising edge of irq 0 pin input is detected interrupt enable register 1 (ienr1) bit 76543210 ienta iens1 ienwp ien4 ien3 ien2 ien1 ien0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w ienr1 is an 8-bit read/write register that enables or disables interrupt requests. bit 7timer a interrupt enable (ienta): bit 7 enables or disables timer a overflow interrupt requests. bit 7: ienta description 0 disables timer a interrupts (initial value) 1 enables timer a interrupts bit 6sci1 interrupt enable (iens1): bit 6 enables or disables sci1 transfer complete interrupt requests. bit 6: iens1 description 0 disables sci1 interrupts (initial value) 1 enables sci1 interrupts bit 5wakeup interrupt enable (ienwp): bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5: ienwp description 0 disables interrupt requests from wkp 7 to wkp 0 (initial value) 1 enables interrupt requests from wkp 7 to wkp 0 70 bits 4 to 0irq 4 to irq 0 interrupt enable (ien4 to ien0): bits 4 to 0 enable or disable irq 4 to irq 0 interrupt requests. bit n: ienn description 0 disables interrupt request irqn (initial value) 1 enables interrupt request irqn (n = 4 to 0) interrupt enable register 2 (ienr2) bit 76543210 iendt ienad iens2 ientg ientfh ientfl ientc ientb initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w ienr2 is an 8-bit read/write register that enables or disables interrupt requests. bit 7direct transfer interrupt enable (iendt): bit 7 enables or disables direct transfer interrupt requests. bit 7: iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6a/d converter interrupt enable (ienad): bit 6 enables or disables a/d converter interrupt requests. bit 6: ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit 5sci2 interrupt enable (iens2): bit 5 enables or disables sci2 transfer complete and transfer abort interrupt requests. bit 5: iens2 description 0 disables sci2 interrupts (initial value) 1 enables sci2 interrupts 71 bit 4timer g interrupt enable (ientg): bit 4 enables or disables timer g input capture and overflow interrupt requests. bit 4: ientg description 0 disables timer g interrupts (initial value) 1 enables timer g interrupts bit 3timer fh interrupt enable (ientfh): bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3: ientfh description 0 disables timer fh interrupts (initial value) 1 enables timer fh interrupts bit 2timer fl interrupt enable (ientfl): bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2: ientfl description 0 disables timer fl interrupts (initial value) 1 enables timer fl interrupts bit 1timer c interrupt enable (ientc): bit 1 enables or disables timer c overflow or underflow interrupt requests. bit 1: ientc description 0 disables timer c interrupts (initial value) 1 enables timer c interrupts bit 0timer b interrupt enable (ientb): bit 0 enables or disables timer b overflow or underflow interrupt requests. bit 0: ientb description 0 disables timer b interrupts (initial value) 1 enables timer b interrupts sci3 interrupt control is covered in 10.4.2, in the description of serial control register 3. 72 interrupt request register 1 (irr1) bit 76543210 irrta irrs1 irri4 irri3 irri2 irri1 irri0 initial value 00100000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. irr1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer a, sci1, or irq 4 to irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7timer a interrupt request flag (irrta) bit 7: irrta description 0 clearing conditions: when irrta = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when the timer a counter value overflows (goes from h'ff to h'00) bit 6sci1 interrupt request flag (irrs1) bit 6: irrs1 description 0 clearing conditions: when irrs1 = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when an sci1 transfer is completed bit 5reserved bit: bit 5 is reserved; it is always read as 1, and cannot be modified. bits 4 to 0irq 4 to irq 0 interrupt request flags (irri4 to irri0) bit n: irrin description 0 clearing conditions: when irrin = 1, it is cleared by writing 0 to irrin (initial value) 1 setting conditions: irrin is set when pin irq n is set to interrupt input, and the designated signal edge is detected (n = 4 to 0) 73 interrupt request register 2 (irr2) bit 76543210 irrdt irrad irrs2 irrtg irrtfh irrtfl irrtc irrtb initial value 00000000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. irr2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct transfer, a/d converter, sci2, timer g, timer fh, timer fl, timer c, or timer b interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7direct transfer interrupt request flag (irrdt) bit 7: irrdt description 0 clearing conditions: when irrdt = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when dton = 1 and a direct transfer is made immediately after a sleep instruction is executed bit 6a/d converter interrupt request flag (irrad) bit 6: irrad description 0 clearing conditions: when irrad = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when a/d conversion is completed and adsf is reset bit 5sci2 interrupt request flag (irrs2) bit 5: irrs2 description 0 clearing conditions: when irrs2 = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when an sci2 transfer is completed or aborted 74 bit 4timer g interrupt request flag (irrtg) bit 4: irrtg description 0 clearing conditions: when irrtg = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when pin tmig is set to tmig input and the designated signal edge is detected bit 3timer fh interrupt request flag (irrtfh) bit 3: irrtfh description 0 clearing conditions: when irrtfh = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when counter fh matches output compare register fh in 8-bit timer mode, or when 16-bit counter f (tcfl, tcfh) matches output compare register f (ocrfl, ocrfh) in 16-bit timer mode bit 2timer fl interrupt request flag (irrtfl) bit 2: irrtfl description 0 clearing conditions: when irrtfl = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when counter fl matches output compare register fl in 8-bit timer mode bit 1timer c interrupt request flag (irrtc) bit 1: irrtc description 0 clearing conditions: when irrtc = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when the timer c counter value overflows (goes from h'ff to h'00) or underflows (goes from h'00 to h'ff) 75 bit 0timer b interrupt request flag (irrtb ) bit 0: irrtb description 0 clearing conditions: when irrtb = 1, it is cleared by writing 0 (initial value) 1 setting conditions: when the timer b counter value overflows (goes from h'ff to h'00) wakeup interrupt request register (iwpr) bit 76543210 iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 initial value 00000000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. iwpr is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins wkp 7 to wkp 0 are set to wakeup input and a pin receives a falling edge input. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bits 7 to 0wakeup interrupt request flags (wkpf7 to wkpf0) bit n: iwpfn description 0 clearing conditions: when iwpfn = 1, it is cleared by writing 0 to iwpfn 1 setting conditions: iwpfn is set when pin wkp n is set to wakeup interrupt input, and a falling edge input is detected at the pin (n = 7 to 0) 3.3.3 external interrupts there are 13 external interrupts, wkp 0 to wkp 7 and irq 0 to irq 4 . interrupts wkp 0 to wkp 7 : interrupts wkp 0 to wkp 7 are requested by falling edge inputs at pins wkp 0 to wkp 7 . when these pins are designated as wkp 0 to wkp 7 pins in port mode register 5 (pmr5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (iwpr) is set to 1, requesting an interrupt. wakeup interrupt requests can be disabled by clearing the ienwp bit in ienr1 to 0. it is also possible to mask all interrupts by setting the ccr i bit to 1. 76 when an interrupt exception handling request is received for interrupts wkp 0 to wkp 7 , the ccr i bit is set to 1. the vector number for interrupts wkp 0 to wkp 7 is 9. since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. interrupts irq 0 to irq 4 : interrupts irq 0 to irq 4 are requested by into pins inputs to irq 0 to irq 4 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg0 to ieg4 in the edge select register (iegr). when these pins are designated as pins irq 0 to irq 4 in port mode registers 1 and 2 (pmr1 and pmr2) and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. interrupts irq 0 to irq 4 can be disabled by clearing bits ien0 to ien4 in ienr1 to 0. all interrupts can be masked by setting the i bit in ccr to 1. when irq 0 to irq 4 interrupt exception handling is initiated, the i bit is set to 1. vector numbers 4 to 8 are assigned to interrupts irq 0 to irq 4 . the order of priority is from irq 0 (high) to irq 4 (low). table 3.2 gives details. 3.3.4 internal interrupts there are 20 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2 to 0. all interrupts can be masked by setting the i bit in ccr to 1. when an internal interrupt request is accepted, the i bit is set to 1. vector numbers 10 to 20 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.3 shows a block diagram of the interrupt controller. figure 3.4 shows the flow up to interrupt acceptance. interrupt operation is described as follows. when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. when the interrupt controller receives an interrupt request, it sets the interrupt request flag. from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. 77 if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.5. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. the i bit of ccr is set to 1, masking all further interrupts. the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.3 block diagram of interrupt controller 78 pc contents saved ccr contents saved i ? 1 i = 0 program execution state no yes yes no notation: pc: ccr: i: program counter condition code register i bit of ccr ieno = 1 no yes iendt = 1 no yes irrdt = 1 no yes branch to interrupt handling routine irrio = 1 no yes ien1 = 1 no yes irri1 = 1 no yes ien2 = 1 no yes irri2 = 1 figure 3.4 flow up to interrupt acceptance 79 pc and ccr saved to stack sp (r7) sp ?1 sp ?2 sp ?3 sp ?4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer * ignored on return from interrupt. notes: ccr ccr * pc h pc l 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. figure 3.5 stack state after completion of interrupt exception handling figure 3.6 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. 80 vector fetch f internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ?2 (6) sp ?4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector address) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.6 interrupt sequence 81 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states waiting time for completion of executing instruction * 1 to 13 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 total 15 to 27 note: * not including eepmov instruction. 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3834 series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @Csp) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.7. 82 pc pc r1l pc sp sp sp h'fefc h'fefd h'feff ? ? ? h l l mov. b r1l, @?7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.7 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored. 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls these pins ( irq 4 to irq 0 , and wkp 7 to wkp 0 ), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. 83 table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri4 when pmr2 bit irq4 is changed from 0 to 1 while pin irq 4 is low and iegr bit ieg4 = 0. when pmr2 bit irq4 is changed from 1 to 0 while pin irq 4 is low and iegr bit ieg4 = 1. irri3 when pmr1 bit irq3 is changed from 0 to 1 while pin irq 3 is low and iegr bit ieg3 = 0. when pmr1 bit irq3 is changed from 1 to 0 while pin irq 3 is low and iegr bit ieg3 = 1. irri2 when pmr1 bit irq2 is changed from 0 to 1 while pin irq 2 is low and iegr bit ieg2 = 0. when pmr1 bit irq2 is changed from 1 to 0 while pin irq 2 is low and iegr bit ieg2 = 1. irri1 when pmr1 bit irq1 is changed from 0 to 1 while pin irq 1 is low and iegr bit ieg1 = 0. when pmr1 bit irq1 is changed from 1 to 0 while pin irq 1 is low and iegr bit ieg1 = 1. irri0 when pmr2 bit irq0 is changed from 0 to 1 while pin irq 0 is low and iegr bit ieg0 = 0. when pmr2 bit irq0 is changed from 1 to 0 while pin irq 0 is low and iegr bit ieg0 = 1. iwpr iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp 7 is low iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp 6 is low iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp 5 is low iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp 4 is low iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp 3 is low iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp 2 is low iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp 1 is low iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp 0 is low 84 figure 3.8 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ? ccr i bit 0 ? figure 3.8 port mode register setting and interrupt request flag clearing procedure 85 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider (1/8) system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc (f ) osc w (f ) w /2 osc /2 w /8 w sub /2 to /8192 /2 w /4 w /8 to /128 w w /16 osc /4 w w f f f f f f f f f f f f f f f f figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are f and f sub . four of the clock signals have names: f is the system clock, f sub is the subclock, f osc is the oscillator clock, and f w is the watch clock. the clock signals available for use by peripheral modules are f /2, f /4, f /8, f /16, f /32, f /64, f /128, f /256, f /512, f /1024, f /2048, f /4096, f /8192, f w , f w /2, f w /4, f w /8, f w /16, f w /32, f w /64, and f w /128. the clock requirements differ from one module to another. 86 4.2 system clock generator clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. connecting a crystal oscillator: figure 4.2 shows a typical method of connecting a crystal oscillator. 1 2 c 1 c 2 osc osc r = 1 m 20% c = c = 12 pf 20% f 12 w r f figure 4.2 typical connection to crystal oscillator figure 4.3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4.1 should be used. c s c 0 r s osc 1 osc 2 l s figure 4.3 equivalent circuit of crystal oscillator table 4.1 crystal oscillator parameters frequency (mhz) 24810 r s (max) 500 w 100 w 50 w 30 w c o (max) 7 pf 7 pf 7 pf 7 pf 87 connecting a ceramic oscillator: figure 4.4 shows a typical method of connecting a ceramic oscillator. 1 2 c 1 c 2 osc osc r = 1 m w 20% c = 30 pf 10% c = 30 pf 10% ceramic oscillator: murata f 1 2 r f figure 4.4 typical connection to ceramic oscillator notes on board design: when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.5 board design of oscillator circuit 88 external clock input method: connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.6 shows a typical connection. 1 2 osc osc external clock input open figure 4.6 external clock input (example) frequency oscillator clock ( f osc ) duty cycle 45% to 55% 4.3 subclock generator connecting a 32.768-khz crystal oscillator: clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal oscillator, as shown in figure 4.7. following the same connection precautions as mentioned in section 4.2.3, notes on board design. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 4.7 typical connection to 32.768-khz crystal oscillator 89 figure 4.8 shows the equivalent circuit of the 32.768-khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k w typ f = 32.768 khz crystal oscillator: 0 s w s mx38t (nihon denpa kogyo) figure 4.8 equivalent circuit of 32.768-khz crystal oscillator 2. inputting an external clock (h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s, h8/3837s only) (1) circuit configuration an external clock is input to the x 1 pin. the x 2 pin should be left open. an example of the connection in this case is shown in figure 4.9. x x 1 2 open external clock input figure 4.9 example of connection when inputting an external clock 90 (2) external clock input a square waveform to the x 1 pin. when using the cpu, timer a, timer c, timer g, or an lcd, with a subclock (?w) clock selected, do not stop the clock supply to the x 1 pin. t xh t xl t xf t xr v ih v il figure 4.10 external subclock timing the dc characteristics and timing of an external clock input to the x 1 pin are shown in table 4.2. table 4.2 dc characteristics and timing (v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to + 75c, unless otherwise specified, including subactive mode) item symbol applicable pin test conditions values min typ max unit notes input high voltage v ih x 1 v cc C0.3 v cc +0.3 v figure 4.10 input low voltage v il C0.3 0.3 external subclock rise time t xr 100 ns figure 4.10 external subclock fall time t xf 100 external subclock oscillation frequency f x 32.768 khz external subclock high width t xh 12.0 s figure 4.10 external subclock low width t xl 12.0 s 91 pin connection when not using subclock: when the subclock is not used, connect pin x 1 to v cc and leave pin x 2 open, as shown in figure 4.9. x x 1 2 v cc open figure 4.9 pin connection when not using subclock 4.4 prescalers the h8/3834 series is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock ( f ) as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768-khz signal divided by 4 ( f w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. prescaler s (pss): prescaler s is a 13-bit counter using the system clock ( f ) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by timer a, timer b, timer c, timer f, timer g, sci1, sci2, sci3, the a/d converter, lcd controller, and 14-bit pwm. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is f osc /16. prescaler w (psw): prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 ( f w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . 92 prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping. 4.5 note on oscillators oscillator characteristics of both the masked rom and ztat? versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 93 section 5 power-down modes 5.1 overview the h8/3834 series has seven modes of operation after a reset. these include six power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the seven operation modes. table 5.1 operation modes operating mode description active (high-speed) mode the cpu runs on the system clock, executing program instructions at high speed active (medium-speed) mode the cpu runs on the system clock, executing program instructions at reduced speed subactive mode the cpu runs on the subclock, executing program instructions at reduced speed sleep mode the cpu halts. on-chip peripheral modules continue to operate on the system clock. subsleep mode the cpu halts. timer a, timer c, timer g, and the lcd controller/driver continue to operate on the subclock. watch mode the cpu halts. the time-base function of timer a and the lcd controller/driver continue to operate on the subclock. standby mode the cpu and all on-chip peripheral modules stop operating all the above operating modes except active (high-speed) mode are referred to as power-down modes. in this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode. figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. 94 reset state program execution state program halt state program halt state active (high-speed) mode power-down mode sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction notes: timer a interrupt, irq interrupt, wkp to wkp interrupts timer a interrupt, timer c interrupt, timer g interrupt, irq to irq interrupts, wkp to wkp interrupts all interrupts irq interrupt, irq interrupt, wkp to wkp interrupts 1. 2. 3. 4. 007 04 07 01 07 2 * 1 * 1 * 4 * 4 * 1 * 3 * 3 * lson = 1, tma3 = 1 lson = 0, mson = 1 lson = 0, mson = 0 ssby = 0, lson = 1, tma3 = 1 ssby = 0, lson = 0 ssby = 1, tma3 = 0, lson = 0 ssby = 1, tma3 = 1 sleep instruction dton = 1 dton = 1 dton = 1 sleep instruction a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that the interrupt is accepted and interrupt handling is performed. : transition caused by exception handling subsleep mode subactive mode watch mode active (medium-speed) mode standby mode details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8. sleep mode figure 5.1 operation mode transition diagram 95 table 5.2 internal state in each operation mode active mode function high speed medium speed sleep mode watch mode subactive mode subsleep mode standby mode system clock oscillator functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions cpu instructions functions functions halted halted functions halted halted operation ram retained retained retained retained registers i/o retained * 1 external irq 0 functions functions functions functions functions functions functions interrupts irq 1 retained * 6 irq 2 retained * 6 irq 3 irq 4 wkp 0 functions functions functions functions functions functions functions wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 peripheral timer a functions functions functions functions * 5 functions * 5 functions * 5 retained module timer b retained retained retained functions timer c functions/ retained * 2 functions/ retained * 2 timer f retained retained timer g functions/ retained * 3 functions/ retained * 3 sci1 functions functions functions retained retained retained retained sci2 sci3 reset reset reset reset pwm functions functions retained retained retained retained retained a/d functions functions functions retained retained retained retained lcd functions functions functions functions/ retained * 4 functions/ retained * 4 functions/ retained * 4 retained notes: 1. register contents held; high-impedance output. 2. functions only if external clock or f w /4 internal clock is selected; otherwise halted and retained. 3. functions only if f w /2 internal clock is selected; otherwise halted and retained. 4. functions only if f w or f w /2 internal clock is selected; otherwise halted and retained. 5. functions when timekeeping time-base function is selected. 6. external interrupt requests are ignored. the interrupt request register contents are not affected. 96 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control register name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'e0 h'fff1 system control register 1 (syscr1) bit 76543210 ssby sts2 sts1 sts0 lson initial value 00000111 read/write r/w r/w r/w r/w r/w syscr1 is an 8-bit read/write register for control of the power-down modes. bit 7software standby (ssby): this bit designates transition to standby mode or watch mode. bit 7: ssby description 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode (initial value) when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode. 1 when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode. when a sleep instruction is executed in subactive mode, a transition is made to watch mode. bits 6 to 4standby timer select 2 to 0 (sts2 to sts0): these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 10 ms. 97 bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 wait time = 8,192 states (initial value) 1 wait time = 16,384 states 1 0 wait time = 32,768 states 1 wait time = 65,536 states 1 ** wait time = 131,072 states note: * dont care bit 3low speed on flag (lson): this bit chooses the system clock ( f ) or subclock ( f sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3: lson description 0 the cpu operates on the system clock ( f ) (initial value) 1 the cpu operates on the subclock ( f sub ) bits 2 to 0reserved bits: these bits are reserved; they are always read as 1, and cannot be modified. system control register 2 (syscr2) bit 76543210 nesel dton mson sa1 sa0 initial value 11100000 read/write r/w r/w r/w r/w r/w syscr2 is an 8-bit read/write register for power-down mode control. bits 7 to 5reserved bits: these bits are reserved; they are always read as 1, and cannot be modified. bit 4noise elimination sampling frequency select (nesel): this bit selects the frequency at which the watch clock signal ( f w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( f osc ) generated by the system clock pulse generator. when f osc = 2 to 10 mhz, clear nesel to 0. bit 4: nesel description 0 sampling rate is f osc /16 (initial value) 1 sampling rate is f osc /4 98 bit 3direct transfer on flag (dton): this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3: dton description 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. (initial value) when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1. bit 2medium speed on flag (mson): after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2: mson description 0 operation is in active (high-speed) mode (initial value) 1 operation is in active (medium-speed) mode bits 1 and 0subactive mode clock select (sa1 and sa0): these bits select the cpu clock rate ( f w /2, f w /4, or f w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1: sa1 bit 0: sa0 description 00 f w /8 (initial value) 1 f w /4 1 * f w /2 note: * dont care 99 5.2 sleep mode 5.2.1 transition to sleep mode the system goes from active mode to sleep mode when a sleep instruction is executed while the ssby and lson bits in system control register 1 (syscr1) are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions other than pwm are operational. the cpu register contents are retained. 5.2.2 clearing sleep mode sleep mode is cleared by an interrupt (timer a, timer b, timer c, timer f, timer g, irq 0 to irq 4 , wkp 0 to wkp 7 , sci1, sci2, sci3, a/d converter) or by input at the res pin. clearing by interrupt: when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit is cleared to 0, and bit tma3 in timer register a (tma) is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. as long as a minimum required voltage is applied, the contents of cpu registers and some on-chip peripheral registers, and data in the on-chip ram, are retained. data in the on-chip ram will be retained as long as the specified ram data retention voltage is supplied. the i/o ports go to the high-impedance state. 100 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 0 , irq 1 , wkp 0 to wkp 7 ) or by input at the res pin. clearing by interrupt: when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2Csts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium- speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. when a crystal oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time of at least 10 ms. table 5.3 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 5 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 1.6 2.0 4.1 8.2 16.4 1 16,384 states 3.2 4.1 8.2 16.4 32.8 1 0 32,768 states 6.6 8.2 16.4 32.8 65.5 1 65,536 states 13.1 16.4 32.8 65.5 131.1 1 ** 131,072 states 26.2 32.8 65.5 131.1 262.1 note: * dont care when an external clock is used any values may be set. normally the minimum time (sts2 = sts1 = sts0 = 0) should be set. 101 5.3.4 transition to standby mode and port pin states the system goes from active (high-speed or medium-speed) mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit is cleared to 0, and bit tma3 in tma is cleared to 0. port pins (except those with their mos pull-up turned on) enter high-impedance state when the transition to standby mode is made. this timing is shown in figure 5.2. f internal data bus port pins sleep instruction fetch next instruction fetch sleep instruction execution internal processing output high-impedance active (high-speed or medium-speed) mode standby mode figure 5.2 transition to standby mode and port pin states 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules other than timer a and the lcd controller is halted. the lcd controller can be selected to operate or to halt. as long as a minimum required voltage is applied, the contents of cpu registers and some registers of the on- chip peripheral modules, and the on-chip ram contents, are retained. i/o ports keep the same states as before the transition. 102 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, irq 0 , wkp 0 to wkp 7 ) or by a input at the res pin. clearing by interrupt: watch mode is cleared when an interrupt is requested. the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2Csts0 has elapsed, a stable clock signal is supplied to the entire chip, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see 5.3.3, oscillator settling time after standby mode is cleared. 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than timer a, timer c, timer g, and the lcd controller is halted. as long as a minimum required voltage is applied, the contents of cpu registers and some registers of the on-chip peripheral modules, and the on-chip ram contents, are retained. i/o ports keep the same states as before the transition. 103 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer c, timer g, irq 0 to irq 4 , wkp 0 to wkp 7 ) or by a low input at the res pin. clearing by interrupt: when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, irq 0 , or wkp 0 to wkp 7 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer c, timer g, irq 0 to irq 4 , or wkp 0 to wkp 7 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a input at the res pin. clearing by sleep instruction: if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see 5.8, direct transfer, below. clearing by res pin: clearing by res pin is the same as for standby mode; see clearing by res pin in section 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are f w /2, f w /4, and f w /8. 104 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the mson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 , or wkp 0 to wkp 7 interrupts in standby mode, timer a, irq 0 , or wkp 0 to wkp 7 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction or by a input at the res pin. clearing by sleep instruction: a transition to standby mode takes place if a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1 when a sleep instruction is executed. sleep mode is entered if both ssby and lson are cleared to 0 when a sleep instruction is executed. direct transfer to active (high-speed) mode or to subactive mode is also possible. see 5.8, direct transfer, below for details. clearing by res pin: when the res pin goes low, the cpu enters the reset state and active (medium-speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode in active (medium-speed) mode, the cpu is clocked at 1/8 the frequency in active (high-speed) mode. 5.8 direct transfer 5.8.1 direct transfer overview the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. 105 if the direct transfer interrupt is disabled in interrupt enable register 2 (ienr2), a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. direct transfer from active (high-speed) mode to active (medium-speed) mode: when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. direct transfer from active (medium-speed) mode to active (high-speed) mode: when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. direct transfer from active (high-speed) mode to subactive mode: when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (high-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. direct transfer from active (medium-speed) mode to subactive mode: when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (medium-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 106 5.8.2 calculation of direct transfer time before transition time required before direct transfer from active (high-speed) mode to active (medium- speed) mode: a direct transfer is made from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1. a direct transfer time, that is, the time from sleep instruction execution to interrupt exception handling completion is calculated by expression (1) below. direct transfer time = (number of states for sleep instruction execution + number of states for internal processing) tcyc before transition + number of states for interrupt exception handling execution tcyc after transition ...... (1) example: direct transfer time for the h8/3834 series = (2 + 1) 2tosc + 14 16tosc = 230 tosc notation: tosc: osc clock cycle time tcyc: system clock ( f ) cycle time time required before direct transfer from active (medium-speed) mode to active (high- speed) mode: a direct transfer is made from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1. a direct transfer time, that is, the time from sleep instruction execution to interrupt exception handling completion is calculated by expression (2) below. direct transfer time = (number of states for sleep instruction execution + number of states for internal processing) tcyc before transition + number of states for interrupt exception handling execution tcyc after transition ...... (2) example: direct transfer time for the h8/3834 series = (2 + 1) 16tosc + 14 2tosc = 76 tosc notation: tosc: osc clock cycle time tcyc: system clock ( f ) cycle time time required before direct transfer from subactive mode to active (high-speed) mode: a direct transfer is made from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1. a direct transfer time, that is, the time from sleep 107 instruction execution to interrupt exception handling completion is calculated by expression (3) below. direct transfer time = (number of states for sleep instruction execution + number of states for internal processing) tsubcyc before transition + (wait time designated by sts2 to sts0 bits in scr + number of states for interrupt exception handling execution) tcyc after transition ...... (3) example: direct transfer time for the h8/3834 series (when cpu clock frequency is f w/8 and wait time is 8192 states) = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( f ) cycle time tsubcyc: subclock ( f sub ) cycle time time required before direct transfer from subactive mode to active (medium-speed) mode: a direct transfer is made from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson and dton bits in syscr2 are set to 1, and the tma3 bit in tma is set to 1. a direct transfer time, that is, the time from sleep instruction execution to interrupt exception handling completion is calculated by expression (4) below. direct transfer time = (number of states for sleep instruction execution + number of states for internal processing) tsubcyc before transition (wait time designated by sts2 to sts0 bits in scr + number of states for interrupt exception handling execution) tcyc after transition ...... (4) example: direct transfer time for the h8/3834 series (when cpu clock frequency is f w/8 and wait time is 8192 states) = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( f ) cycle time tsubcyc: subclock ( f sub ) cycle time 108 109 section 6 rom 6.1 overview the h8/3832 has 16 kbytes of on-chip rom, while the h8/3833 has 24 kbytes, the h8/3834 has 32 kbytes, the h8/3835 has 40 kbytes, the h8/3836 has 48 kbytes, and the h8/3837 has 60 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. the ztat? versions of the h8/3834 and h8/3837 each have 32 kbytes and 60 kbytes of prom. with regard to ztat versions of the h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s, and h8/3837s, the ztat versions of the h8/3834 and h8/3837 should be used. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. h'7ffe h'7fff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'7ffe h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom figure 6.1 rom block diagram (h8/3834) 110 6.2 h8/3834 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c256. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb 4 /an 4 low level pb 5 /an 5 pb 6 /an 6 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 28 pins, as listed in table 6.2. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map. table 6.2 socket adapter package socket adapter 100-pin (fp-100b) hs3834esh01h 100-pin (fp-100a) hs3834esf01h 100-pin (tfp-100b) hs3834esn01h 111 h8/3834 eprom socket pin res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 p7 1 v cc av cc test x 1 pb 6 md0 p1 1 p1 2 p1 3 v ss av ss pb 4 pb 5 p1 4 p1 5 p1 6 hn27c256 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 14 fp-100b 9 44 45 46 47 48 49 50 51 67 66 65 64 63 62 61 60 52 88 54 55 56 57 58 59 53 31, 76 89 3 5 96 10 78 79 80 6, 27 2 94 95 81 82 83 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ce oe v cc v ss note: pins not indicated in the figure should be left open. fp-100a 12 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 91 57 58 59 60 61 62 56 34, 79 92 6 8 99 13 81 82 83 9, 30 5 97 98 84 85 86 figure 6.2 socket adapter pin correspondence (with hn27c256) 112 on-chip prom h'0000 h'7fff h'0000 h'7fff address in mcu mode address in prom mode figure 6.3 h8/3834 memory map in prom mode note: when programming with a prom programmer, be sure to specify addresses from h'0000 to h'7fff. 113 6.3 h8/3834 programming the write, verify, and other modes are selected as shown in table 6.3 in h8/3834 prom mode. table 6.3 mode selection in h8/3834 prom mode pin mode ce oe v pp v cc eo 7 to eo 0 ea 14 to ea 0 write l h v pp v cc data input address input verify h l v pp v cc data output address input programming disabled h h v pp v cc high impedance address input notation: l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading the on-chip prom are identical to those for the standard hn27c256 eprom. 6.3.1 writing and verifying an efficient, high-performance programming method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. h'ff data is written in unused address areas. the basic flow of this high-performance programming method is shown in figure 6.4. table 6.4 and table 6.5 give the electrical characteristics in programming mode. figure 6.5 shows a write/verify timing diagram. 114 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n ? write time t = 1 ms 5% pw verify write time t = 3n ms opw last address? all addresses read? address + 1 address ? error end set read mode v = 5.0 v 0.5 v, v = v cc pp cc n < 25 yes no yes no no yes go no go figure 6.4 high-performance programming flowchart 115 table 6.4 dc characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min typ max unit test conditions input high- level voltage eo 7 to eo 0 , ea 14 to ea 0 , oe , ce v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 14 to ea 0 , oe , ce v il C0.3 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 v i oh = C200 a output low- level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 14 to ea 0 , oe , ce |i li | 2 av in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 116 table 6.5 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25c 5c) item symbol min typ max unit test conditions address setup time t as 2 s figure 6.5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 0 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.95 1.0 1.05 ms ce pulse width for overwrite programming t opw * 3 2.85 78.7 ms v cc setup time t vcs 2 s data output delay time t oe 0 500 ns notes: 1. input pulse level: 0.8 v to 2.2 v input rise time/fall time 20 ns timing reference levels: input: 1.0 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.4 high-performance programming flow chart. 117 address data v pp v cc ce oe v pp v cc v cc +1 v cc t as t ds t vps t vcs t pw t opw * t oes t oe t dh t df t ah input data output data write verify note: * t opw is defined by the value given in figure 6-4 high-performance programming flow chart. figure 6.5 prom write/verify timing 6.3.2 programming precautions use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to hitachi specifications for the hn27c256 will result in a correct v pp of 12.5 v. make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. avoid touching the socket adapter or chip during programming, since this may cause contact faults and write errors. 118 6.4 h8/3837 prom mode 6.4.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.6 shows how to set the chip to prom mode. table 6.6 setting to prom mode pin name setting test high level pb 4 /an 4 low level pb 5 /an 5 pb 6 /an 6 high level 6.4.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins, as listed in table 6.7. figure 6.6 shows the pin-to-pin wiring of the socket adapter. figure 6.7 shows a memory map. table 6.7 socket adapter package socket adapter 100-pin (fp-100b) hs3836esh01h 100-pin (fp-100a) hs3836esf01h 100-pin (tfp-100b) hs3836esn01h 119 h8/3837 fp-100a 12 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 91 57 58 59 60 61 84 85 62 56 83 34, 79 92 6 8 99 13 81 82 86 9, 30 5 97 98 fp-100b 9 44 45 46 47 48 49 50 51 67 66 65 64 63 62 61 60 52 88 54 55 56 57 58 81 82 59 53 80 31, 76 89 3 5 96 10 78 79 83 6, 27 2 94 95 pin res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p1 4 p7 7 p7 1 p1 3 v cc av cc test x 1 pb 6 md0 p1 1 p1 2 p1 6 v ss av ss pb 4 pb 5 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss hn27c101 (32 pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 eprom socket note: pins not indicated in the figure should be left open. p1 5 figure 6.6 socket adapter pin correspondence (with hn27c101) 120 on-chip prom missing area h'0000 h'edff h'0000 h'edff h'1ffff address in mcu mode address in prom mode * note: * if read in prom mode, this address area returns unpredictable output data. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if address h'ee00 and higher addresses are programmed by mistake, it may become impossible to program the prom or verify the programmed data. when programming, assign h'ff data to this address area (h'ee00 to h'1ffff). figure 6.7 h8/3837 memory map in prom mode 121 6.5 h8/3837 programming the write, verify, and other modes are selected as shown in table 6.8 in h8/3837 prom mode. table 6.8 mode selection in h8/3837 prom mode pin mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled lhh hl l hhh notation: l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading the on-chip prom are identical to those for the standard hn27c101 eprom. page programming is not supported, however. the prom writer must not be set to page mode. a prom programmer that provides only page programming mode cannot be used. when selecting a prom programer, check that it supports a byte-by-byte high- speed, high-reliability programming method. be sure to set the address range to h'0000 to h'edff. 6.5.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.8. 122 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n ? pw verify write time t = 0.2n ms opw last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc all addresses read? end error n 25 < address + 1 address ? no yes no go go yes no no yes write time t = 0.2 ms 5% figure 6.8 high-speed, high-reliability programming flow chart 123 table 6.9 and table 6.10 give the electrical characteristics in programming mode. table 6.9 dc characteristics (preliminary) (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min typ max unit test conditions input high- level voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v il C0.3 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 v i oh = C200 a output low- level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm |i li | 2 av in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 124 table 6.10 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25c 5c) item symbol min typ max unit test conditions address setup time t as 2 s figure 6.9 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms v cc setup time t vcs 2 s ce setup time t ces 2 s data output delay time t oe 0 200 ns notes: 1. input pulse level: 0.45 v to 2.4 v input rise time/fall time 20 ns timing reference levels: input: 0.8 v, 2.0 v output:0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.8 high-speed, high-reliability programming flow chart. 125 figure 6.9 shows a write/verify timing diagram. address data v pp v cc ce pgm oe v pp v cc v +1 cc v cc write verify input data output data t as t ds t vps t vcs t ces t pw t opw * t dh t oes t oe t df t ah note: * t opw is defined by the value given in figure 6-8 high-speed, high-reliability programming flow chart. figure 6.9 prom write/verify timing 126 6.5.2 programming precautions use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to hitachi specifications for the hn27c101 will result in correct v pp of 12.5 v. make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. select the programming mode carefully. the chip cannot be programmed in page programming mode. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if address h'ee00 and higher addresses are programmed by mistake, it may become impossible to program the prom or verify the programmed data. when programming, assign h'ff data to the address area from h'ee00 to h'1ffff. 127 6.6 reliability of programmed data a highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150c. high-temperature baking is a screening method that quickly eliminates prom memory cells prone to initial data retention failure. figure 6.10 shows a flowchart of this screening procedure. install write program and verify contents bake at high temperature with power off 125 c to 150 c, 24 hrs to 48 hrs read and check program figure 6.10 recommended screening procedure if write errors occur repeatedly while the same prom programmer is being used, stop programming and check for problems in the prom programmer and socket adapter, etc. please notify your hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 128 129 section 7 ram 7.1 overview the h8/3832, h8/3833 and h8/3834 have 1 kbyte of high-speed static ram on-chip, while the h8/3835, h8/3836, and h8/3837 each have 2 kbytes. the ram is connected to the cpu by a 16- bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'fb82 h'fb80 h'fb80 h'fb82 h'fb81 h'fb83 on-chip ram figure 7.1 ram block diagram (h8/3834) 130 131 section 8 i/o ports 8.1 overview the h8/3834 series is provided with eight 8-bit i/o ports, one 4-bit i/o port, one 3-bit i/o port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. ports 5, 6, 7, 8, 9, and a double as liquid crystal display segment pins and common pins. the choice of pin functions can be made in 4-bit groupings. block diagrams of each port are given in appendix c, i/o port block diagrams. table 8.1 port functions port description pins other functions function switching register port 1 8-bit i/o port input pull-up mos option p1 7 to p1 5 / irq 3 to irq 1 / tmif, tmic, tmib external interrupts 3 to 1 timer event input tmif, tmic, tmib pmr1 tcrf, tmc, tmb p1 4 /pwm 14-bit pwm output pmr1 p1 3 /tmig timer g input capture pmr1 p1 2 , p1 1 / tmofh, tmofl timer f output compare pmr1 p1 0 /tmow timer a clock output pmr1 port 2 8-bit i/o port p2 7 to p2 2 none open drain output option p2 1 /ud timer c count-up/down selection pmr2 high-current port p2 0 / irq 4 / adtrg external interrupt 4 and a/d converter external trigger pmr2 amr 132 table 8.1 port functions (cont) port description pins other functions function switching register port 3 8-bit i/o port input pull-up mos option high-current port p3 7 / cs p3 6 /strb p3 5 /so 2 p3 4 /si 2 p3 3 /sck 2 sci2 chip select input ( cs ), strobe output (strb), data output (so 2 ), data input (si 2 ), clock input/output (sck 2 ) pmr3 p3 2 /so 1 p3 1 /si 1 p3 0 /sck 1 sci1 data output (so 1 ), data input (si 1 ), clock input/output (sck 1 ) pmr3 port 4 1-bit input-only port p4 3 / irq 0 external interrupt 0 pmr2 3-bit i/o port p4 2 /txd p4 1 /rxd p4 0 /sck 3 sci3 data output (txd), data input (rxd), clock input/output (sck 3 ) scr3 smr3 port 5 8-bit i/o port input pull-up mos option p5 7 to p5 0 / wkp 7 to wkp 0 / seg 8 to seg 1 wakeup input ( wkp 7 to wkp 0 ) segment output (seg 8 to seg 1 ) pmr5 lpcr port 6 8-bit i/o port input pull-up mos option p6 7 to p6 0 / seg 16 to seg 9 segment output (seg 16 to seg 9 ) lpcr port 7 8-bit i/o port p7 7 to p7 0 / seg 24 to seg 17 segment output (seg 24 to seg 17 ) lpcr port 8 8-bit i/o port p8 7 to p8 0 / seg 32 to seg 25 segment output (seg 32 to seg 25 ) lpcr port 9 8-bit i/o port p9 7 /seg 40 /cl 1 p9 6 /seg 39 /cl 2 p9 5 /seg 38 /do p9 4 /seg 37 /m p9 3 to p9 0 / seg 36 to seg 33 segment output (seg 40 to seg 37 ) latch clock (cl 1 ), for external segment expansion, shift clock (cl 2 ), display data port (do), and alternating signal (m) segment output (seg 36 to seg 33 ) lpcr port a 4-bit i/o port pa 3 to pa 0 / com 4 to com 1 common output (com 4 to com 1 ) lpcr port b 8-bit input port pb 7 to pb 0 / an 7 to an 0 a/d converter analog input amr port c 4-bit input port pc 3 to pc 0 / an 11 to an 8 a/d converter analog input amr 133 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. figure 8.1 shows its pin configuration. p1 / irq /tmif p1 / irq /tmic p1 / irq /tmib p1 /pwm p1 /tmig p1 /tmofh p1 /tmofl p1 /tmow 7 6 5 4 3 2 1 0 3 2 1 port 1 figure 8.1 port 1 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbrev. r/w initial value address port data register 1 pdr1 r/w h'00 h'ffd4 port control register 1 pcr1 w h'00 h'ffe4 port pull-up control register 1 pucr1 r/w h'00 h'ffe0 port mode register 1 pmr1 r/w h'00 h'ffc8 134 port data register 1 (pdr1) bit 76543210 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr1 is an 8-bit register that stores data for pins p1 7 through p1 0 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. upon reset, pdr1 is initialized to h'00. port control register 1 (pcr1) bit 76543210 pcr1 7 pcr1 6 pcr1 5 pcr1 4 pcr1 3 pcr1 2 pcr1 1 pcr1 0 initial value 00000000 read/write wwwwwwww pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 to p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'00. pcr1 is a write-only register. all bits are read as 1. port pull-up control register 1 (pucr1) bit 76543210 pucr1 7 pucr1 6 pucr1 5 pucr1 4 pucr1 3 pucr1 2 pucr1 1 pucr1 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr1 controls whether the mos pull-up of each port 1 pin is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr1 is initialized to h'00. 135 port mode register 1 (pmr1) bit 76543210 irq3 irq2 irq1 pwm tmig tmofh tmofl tmow initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. upon reset, pmr1 is initialized to h'00. bit 7p1 7 / irq 3 /tmif pin function switch (irq3): this bit selects whether pin p1 7 / irq 3 /tmif is used as p1 7 or as irq 3 /tmif. bit 7: irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /tmif input pin note: rising or falling edge sensing can be designated for irq 3 /tmif. for details on tmif pin settings, see 9.5.2 (3), timer control register f (tcrf). bit 6p1 6 / irq 2 /tmic pin function switch (irq2): this bit selects whether pin p1 6 / irq 2 /tmic is used as p1 6 or as irq 2 /tmic. bit 6: irq2 description 0 functions as p1 6 i/o pin (initial value) 1 functions as irq 2 /tmic input pin note: rising or falling edge sensing can be designated for irq 2 /tmic. for details on tmic pin settings, see 9.4.2 (1), timer mode register c (tmc). bit 5p1 5 / irq 1 /tmib pin function switch (irq1): this bit selects whether pin p1 5 / irq 1 /tmib is used as p1 5 or as irq 1 /tmib. bit 5: irq1 description 0 functions as p1 5 i/o pin (initial value) 1 functions as irq 1 /tmib input pin note: rising or falling edge sensing can be designated for irq 1 /tmib. for details on tmib pin settings, see 9.3.2 (1), timer mode register b (tmb). 136 bit 4p1 4 /pwm pin function switch (pwm): this bit selects whether pin p1 4 /pwm is used as p1 4 or as pwm. bit 4: pwm description 0 functions as p1 4 i/o pin (initial value) 1 functions as pwm output pin bit 3p1 3 /tmig pin function switch (tmig): this bit selects whether pin p1 3 /tmig is used as p1 3 or as tmig. bit 3: tmig description 0 functions as p1 3 i/o pin (initial value) 1 functions as tmig input pin bit 2p1 2 /tmofh pin function switch (tmofh): this bit selects whether pin p1 2 /tmofh is used as p1 2 or as tmofh. bit 2: tmofh description 0 functions as p1 2 i/o pin (initial value) 1 functions as tmofh output pin bit 1: p1 1 /tmofl pin function switch (tmofl) this bit selects whether pin p1 1 /tmofl is used as p1 1 or as tmofl. bit 1: tmofl description 0 functions as p1 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0p1 0 /tmow pin function switch (tmow): this bit selects whether pin p1 0 /tmow is used as p1 0 or as tmow. bit 0: tmow description 0 functions as p1 0 i/o pin (initial value) 1 functions as tmow output pin 137 8.2.3 pin functions table 8.3 shows the port 1 pin functions. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 / irq 3 /tmif the pin function depends on bit irq3 in pmr1, bits cksl2 to cksl0 in tcrf, and bit pcr1 7 in pcr1. irq3 0 1 pcr1 7 01 * cksl2 to cksl0 * not 0 ** 0 ** pin function p1 7 input pin p1 7 output pin irq 3 input pin irq 3 /tmif input pin note: when using as tmif input pin, clear bit ien3 in ienr1 to 0, disabling irq 3 interrupts. p1 6 / irq 2 /tmic the pin function depends on bit irq2 in pmr1, bits tmc2 to tmc0 in tmc, and bit pcr1 6 in pcr1. irq2 0 1 pcr1 6 01 * tmc2 to tmc0 * not 111 111 pin function p1 6 input pin p1 6 output pin irq 2 input pin irq 2 /tmic input pin note: when using as tmic input pin, clear bit ien2 in ienr1 to 0, disabling irq 2 interrupts. p1 5 / irq 1 /tmib the pin function depends on bit irq1 in pmr1, bits tmb2 to tmb0 in tmb, and bit pcr1 5 in pcr1. irq1 0 1 pcr1 5 01 * tmb2 to tmb0 * not 111 111 pin function p1 5 input pin p1 5 output pin irq 1 input pin irq 1 /tmib input pin note: when using as tmib input pin, clear bit ien1 in ienr1 to 0, disabling irq1 interrupts. note: * dont care 138 table 8.3 port 1 pin functions (cont) pin pin functions and selection method p1 4 /pwm the pin function depends on bit pwm in pmr1 and bit pcr1 4 in pcr1. pwm 0 1 pcr1 4 01 * pin function p1 4 input pin p1 4 output pin pwm output pin p1 3 /tmig the pin function depends on bit tmig in pmr1 and bit pcr1 3 in pcr1. tmig 0 1 pcr1 3 01 * pin function p1 3 input pin p1 3 output pin tmig input pin p1 2 /tmofh the pin function depends on bit tmofh in pmr1 and bit pcr1 2 in pcr1. tmofh 0 1 pcr1 2 01 * pin function p1 2 input pin p1 2 output pin tmofh output pin p1 1 /tmofl the pin function depends on bit tmofl in pmr1 and bit pcr1 1 in pcr1. tmofl 0 1 pcr1 1 01 * pin function p1 1 input pin p1 1 output pin tmofl output pin p1 0 /tmow the pin function depends on bit tmow in pmr1 and bit pcr1 0 in pcr1. tmow 0 1 pcr1 0 01 * pin function p1 0 input pin p1 0 output pin tmow output pin note: * dont care 139 8.2.4 pin states table 8.4 shows the port 1 pin states in each operating mode. table 8.4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 / irq 3 /tmif p1 6 / irq 2 /tmic p1 5 / irq 1 /tmib p1 4 /pwm p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 01 pucr1 n 01 * mos input pull-up off on off note: * dont care n = 7 to 4 140 8.3 port 2 8.3.1 overview port 2 is an 8-bit i/o port. figure 8.2 shows its pin configuration. p2 p2 p2 p2 p2 p2 p2 /ud p2 / irq / adtrg 7 6 5 4 3 2 1 0 port 2 4 figure 8.2 port 2 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 2 register configuration. table 8.5 port 2 registers name abbrev. r/w initial value address port data register 2 pdr2 r/w h'00 h'ffd5 port control register 2 pcr2 w h'00 h'ffe5 port mode register 2 pmr2 r/w h'c0 h'ffc9 port mode register 4 pmr4 r/w h'00 h'ffcb 141 port data register 2 (pdr2) bit 76543210 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr2 is an 8-bit register that stores data for pins p2 7 through p2 0 . if port 2 is read while pcr2 bits are set to 1, the values stored in pdr2 are read, regardless of the actual pin states. if port 2 is read while pcr2 bits are cleared to 0, the pin states are read. upon reset, pdr2 is initialized to h'00. port control register 2 (pcr2) bit 76543210 pcr2 7 pcr2 6 pcr2 5 pcr2 4 pcr2 3 pcr2 2 pcr2 1 pcr2 0 initial value 00000000 read/write wwwwwwww pcr2 is an 8-bit register for controlling whether each of the port 2 pins p2 7 to p2 0 functions as an input pin or output pin. setting a pcr2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr2 and in pdr2 are valid only when the corresponding pin is designated in pmr2 as a general i/o pin. upon reset, pcr2 is initialized to h'00. pcr2 is a write-only register. all bits are read as 1. port mode register 2 (pmr2) bit 76543210 pof2 ncs irq0 pof1 ud irq4 initial value 11000000 read/write r/w r/w r/w r/w r/w r/w pmr2 is an 8-bit read/write register, controlling the selection of pin functions for pins p2 0 , p2 1 ,and p4 3 , controlling the pmos on/off option for pins p3 5 /so 2 and p3 2 /so 1 , and controlling the tmig input noise canceller. upon reset, pmr2 is initialized to h'c0. 142 bits 7 to 6reserved bits: bits 7 to 6 are reserved; they are always read as 1, and cannot be modified. bit 5p3 5 /so 2 pin pmos control (pof2): this bit controls the on/off state of the pmos transistor in the p3 5 /so 2 pin output buffer. bit 5: pof2 description 0 cmos output (initial value) 1 nmos open-drain output bit 4tmig noise canceller select (ncs): this bit controls the noise canceller circuit for input capture at pin tmig. bit 4: ncs description 0 noise canceller function not selected (initial value) 1 noise canceller function selected bit 3p4 3 / irq 0 pin function switch (irq0): this bit selects whether pin p4 3 / irq 0 is used as p4 3 or as irq 0 . bit 3: irq0 description 0 functions as p4 3 input pin (initial value) 1 functions as irq 0 input pin bit 2p3 2 /so 1 pin pmos control (pof1): this bit controls the on/off state of the pmos transistor in the p3 2 /so 1 pin output buffer. bit 2: pof1 description 0 cmos output (initial value) 1 nmos open-drain output bit 1p2 1 /ud pin function switch (ud): this bit selects whether pin p2 1 /ud is used as p2 1 or as ud. bit 1: ud description 0 functions as p2 1 i/o pin (initial value) 1 functions as ud input pin 143 bit 0: p2 0 / irq 4 / adtrg pin function switch (irq4): this bit selects whether pin p2 0 / irq 4 / adtrg is used as p2 0 or as irq 4 / adtrg . bit 0: irq4 description 0 functions as p2 0 i/o pin (initial value) 1 functions as irq 4 / adtrg input pin note: see 12.3.2, start of a/d conversion by external trigger input, for the adtrg pin setting. port mode register 4 (pmr4) bit 76543210 nmod 7 nmod 6 nmod 5 nmod 4 nmod 3 nmod 2 nmod 1 nmod 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr4 is an 8-bit read/write register, used to select cmos output or nmos open drain output for each port 2 pin. upon reset, pmr4 is initialized to h'00. bit nnmos open-drain output select (nmodn): this bit selects nmos open-drain output when pin p2 n is used as an output pin. bit n: nmodn description 0 cmos output 1 nmos open-drain outputnmos open-drain output (n = 7 to 0) 144 8.3.3 pin functions table 8.6 shows the port 2 pin functions. table 8.6 port 2 pin functions pin pin functions and selection method p2 7 to p2 2 input or output is selected as follows by the bit settings in pcr2. (n = 2 to 7) pcr2n 0 1 pin function p2 n input pin p2 n output pin p2 1 /ud the pin function depends on bit ud in pmr2 and bit pcr2 1 in pcr2. ud 0 1 pcr2 1 01 * pin function p2 1 input pin p2 1 output pin ud input pin p2 0 / irq 4 / adtrg the pin function depends on bit irq4 in pmr2, bit trge in amr, and bit pcr2 0 in pcr2. irq4 0 1 pcr2 0 01 * trge * 01 pin function p2 0 input pin p2 0 output pin irq 4 input pin irq 4 / adtrg input pin note: when using as adtrg input pin, clear bit ien4 in ienr1 to 0, disabling irq 4 interrupts. note: * dont care 8.3.4 pin states table 8.7 shows the port 2 pin states in each operating mode. table 8.7 port 2 pin states pins reset sleep subsleep standby watch subactive active p2 7 to p2 2 p2 1 /ud p2 0 / irq 4 / adtrg high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 145 8.4 port 3 8.4.1 overview port 3 is an 8-bit i/o port, configured as shown in figure 8.3. p3 / cs p3 /strb p3 /so p3 /si p3 /sck p3 /so p3 /si p3 /sck 7 6 5 4 3 2 1 0 2 port 3 1 1 1 2 2 figure 8.3 port 3 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 3 register configuration. table 8.8 port 3 registers name abbrev. r/w initial value address port data register 3 pdr3 r/w h'00 h'ffd6 port control register 3 pcr3 w h'00 h'ffe6 port pull-up control register 3 pucr3 r/w h'00 h'ffe1 port mode register 3 pmr3 r/w h'00 h'ffca 146 port data register 3 (pdr3) bit 76543210 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 0 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. upon reset, pdr3 is initialized to h'00. port control register 3 (pcr3) bit 76543210 pcr3 7 pcr3 6 pcr3 5 pcr3 4 pcr3 3 pcr3 2 pcr3 1 pcr3 0 initial value 00000000 read/write wwwwwwww pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 0 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. upon reset, pcr3 is initialized to h'00. pcr3 is a write-only register. all bits are read as 1. port pull-up control register 3 (pucr3) bit 76543210 pucr3 7 pucr3 6 pucr3 5 pucr3 4 pucr3 3 pucr3 2 pucr3 1 pucr3 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr3 bits control the on/off state of pin p3 7 Cp3 0 mos pull-ups. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr3 is initialized to h'00. 147 port mode register 3 (pmr3) bit 76543210 cs strb so2 si2 sck2 so1 si1 sck1 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. upon reset, pmr3 is initialized to h'00. bit 7p3 7 / cs pin function switch (cs): this bit selects whether pin p3 7 / cs is used as p3 7 or as cs . bit 7: cs description 0 functions as p3 7 i/o pin (initial value) 1 functions as cs input pin bit 6p3 6 /strb pin function switch (strb): this bit selects whether pin p3 6 /strb is used as p3 6 or as strb. bit 6: strb description 0 functions as p3 6 i/o pin (initial value) 1 functions as strb output pin bit 5p3 5 /so 2 pin function switch (so2): this bit selects whether pin p3 5 /so 2 is used as p3 5 or as so 2 . bit 5: so2 description 0 functions as p3 5 i/o pin (initial value) 1 functions as so 2 output pin bit 4p3 4 /si 2 pin function switch (si2): this bit selects whether pin p3 4 /si 2 is used as p3 4 or as si 2 . bit 4: si2 description 0 functions as p3 4 i/o pin (initial value) 1 functions as si 2 input pin 148 bit 3p3 3 /sck 2 pin function switch (sck2): this bit selects whether pin p3 3 /sck 2 is used as p3 3 or as sck 2 . bit 3: sck2 description 0 functions as p3 3 i/o pin (initial value) 1 functions as sck 2 i/o pin bit 2p3 2 /so 1 pin function switch (so1): this bit selects whether pin p3 2 /so 1 is used as p3 2 or as so 1 . bit 2: so1 description 0 functions as p3 2 i/o pin (initial value) 1 functions as so 1 output pin bit 1p3 1 /si 1 pin function switch (si1): this bit selects whether pin p3 1 /si 1 is used as p3 1 or as si 1 . bit 1: si1 description 0 functions as p3 1 i/o pin (initial value) 1 functions as si 1 input pin bit 0p3 0 /sck 1 pin function switch (sck1): this bit selects whether pin p3 0 /sck 1 is used as p3 0 or as sck 1 . bit 0: sck1 description 0 functions as p3 0 i/o pin (initial value) 1 functions as sck 1 i/o pin 149 8.4.3 pin functions table 8.9 shows the port 3 pin functions. table 8.9 port 3 pin functions pin pin functions and selection method p3 7 / cs the pin function depends on bit cs in pmr3 and bit pcr3 7 in pcr3. cs 0 1 pcr3 7 01 * pin function p3 7 input pin p3 7 output pin cs input pin p3 6 /strb the pin function depends on bit strb in pmr3 and bit pcr3 6 in pcr3. strb 0 1 pcr3 6 01 * pin function p3 6 input pin p3 6 output pin strb output pin p3 5 /so 2 the pin function depends on bit so2 in pmr3 and bit pcr3 5 in pcr3. so2 0 1 pcr3 5 01 * pin function p3 5 input pin p3 5 output pin so 2 output pin p3 4 /si 2 the pin function depends on bit si2 in pmr3 and bit pcr3 4 in pcr3. si2 0 1 pcr3 4 01 * pin function p3 4 input pin p3 4 output pin si 2 input pin p3 3 /sck 2 the pin function depends on bit sck2 in pmr3, bits cks2 to 0 in scr2, and bit pcr3 3 in pcr3. sck2 0 1 cks2 to cks0 * not 111 111 pcr3 3 01 * * pin function p3 3 input pin p3 3 output pin sck 2 output pin sck 2 input pin note: * dont care 150 table 8.9 port 3 pin functions (cont) pin pin functions and selection method p3 2 /so 1 the pin function depends on bit so1 in pmr3 and bit pcr3 2 in pcr3. so1 0 1 pcr3 2 01 * pin function p3 2 input pin p3 2 output pin so 1 output pin p3 1 /si 1 the pin function depends on bit si1 in pmr3 and bit pcr3 1 in pcr3. si1 0 1 pcr3 1 01 * pin function p3 1 input pin p3 1 output pin si 1 input pin p3 0 /sck 1 the pin function depends on bit sck1 in pmr3, bit cks3 in scr1, and bit pcr3 0 in pcr3. sck1 0 1 cks3 * 01 pcr3 0 01 ** pin function p3 0 input pin p3 0 output pin sck 1 output pin sck 1 input pin note: * dont care 151 8.4.4 pin states table 8.10 shows the port 3 pin states in each operating mode. table 8.10 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 / cs p3 6 /strb p3 5 /so 2 p3 4 /si 2 p3 3 /sck 2 p3 2 /so 1 p3 1 /si 1 p3 0 /sck 1 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.4.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 01 pucr3 n 01 * mos input pull-up off on off note: * dont care n = 7 to 0 152 8.5 port 4 8.5.1 overview port 4 consists of a 3-bit i/o port and a 1-bit input port, and is configured as shown in figure 8.4. p4 / irq p4 /txd p4 /rxd p4 /sck 3 2 1 0 port 4 3 0 figure 8.4 port 4 pin configuration 8.5.2 register configuration and description table 8.11 shows the port 4 register configuration. table 8.11 port 4 registers name abbrev. r/w initial value address port data register 4 pdr4 r/w h'f8 h'ffd7 port control register 4 pcr4 w h'f8 h'ffe7 153 port data register 4 (pdr4) bit 76543210 p4 3 p4 2 p4 1 p4 0 initial value 11111000 read/write rr/wr/wr/w pdr4 is an 8-bit register that stores data for port 4 pins p4 2 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'f8. port control register 4 (pcr4) bit 76543210 pcr4 2 pcr4 1 pcr4 0 initial value 11111000 read/write www pcr4 controls whether each of the port 4 pins p4 2 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr4 and in pdr4 are valid only when the corresponding pin is designated in scr3 as a general i/o pin. upon reset, pcr4 is initialized to h'f8. pcr4 is a write-only register. all bits are read as 1. 154 8.5.3 pin functions table 8.12 shows the port 4 pin functions. table 8.12 port 4 pin functions pin pin functions and selection method p4 3 / irq 0 the pin function depends on the irq0 bit setting in pmr2. irq0 0 1 pin function p4 3 input pin irq 0 input pin p4 2 /txd the pin function depends on bit te in scr3 and bit pcr4 2 in pcr4. te 0 1 pcr4 2 01 * pin function p4 2 input pin p4 2 output pin txd output pin p4 1 /rxd the pin function depends on bit re in scr3 and bit pcr4 1 in pcr4. re 0 1 pcr4 1 01 * pin function p4 1 input pin p4 1 output pin rxd input pin p4 0 /sck 3 the pin function depends on bits cke1 and cke0 in scr3, bit com in smr, and bit pcr4 0 in pcr4. cke1 0 1 cke0 0 1 * com 0 1 ** pcr4 0 01 ** pin function p4 0 input pin p4 0 output pin sck 3 output pin sck 3 input pin note: * dont care 155 8.5.4 pin states table 8.13 shows the port 4 pin states in each operating mode. table 8.13 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 3 / irq 0 p4 2 /txd p4 1 /rxd p4 0 /sck 3 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.6 port 5 8.6.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.5. p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg p5 / wkp /seg 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 5 8 7 6 5 4 3 2 1 figure 8.5 port 5 pin configuration 156 8.6.2 register configuration and description table 8.14 shows the port 5 register configuration. table 8.14 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffe2 port mode register 5 pmr5 r/w h'00 h'ffcc port data register 5 (pdr5) bit 76543210 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. port control register 5 (pcr5) bit 76543210 pcr5 7 pcr5 6 pcr5 5 pcr5 4 pcr5 3 pcr5 2 pcr5 1 pcr5 0 initial value 00000000 read/write wwwwwwww pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr5 and in pdr5 are valid only when the corresponding pin is designated as a general i/o pin in pmr5 and in bits sgs3 to sgs0 of lpcr. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register. all bits are read as 1. 157 port pull-up control register 5 (pucr5) bit 76543210 pucr5 7 pucr5 6 pucr5 5 pucr5 4 pucr5 3 pucr5 2 pucr5 1 pucr5 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr5 bits control the on/off state of pin p5 7 Cp5 0 mos pull-ups. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00. port mode register 5 (pmr5) bit 76543210 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit np5 n / wkp n /seg n+1 pin function switch (wkpn): when pin p5 n / wkp n /seg n+1 is not used as a seg n+1 pin, this bit selects whether it is used as p5 n or as wkp n . bit n: wkpn description 0 functions as p5 n i/o pin (initial value) 1 functions as wkp n input pin (n = 7 to 0) note: for information on use as a seg n+1 pin, see 13.2.1, lcd port control register (lpcr). 158 8.6.3 pin functions table 8.15 shows the port 5 pin functions. table 8.15 port 5 pin functions pin pin functions and selection method p5 7 / wkp 7 / seg 8 to p5 4 / wkp 4 /seg 5 the pin function depends on bit wkpn in pmr5, bit pcr5 n in pcr5, and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 0 *** 1 *** wkpn 0 1 * pcr5 n 01 ** pin function p5 n input pin p5 n output pin wkp n input pin seg n+1 output pin p5 3 / wkp 3 / seg 4 to p5 0 / wkp 0 /seg 1 the pin function depends on bit wkp n in pmr5, bit pcr5n in pcr5, and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) sgs3 to sgs0 0 *** or 1 ** 01 ** 1 wkpn 0 1 * pcr5n 0 1 * * pin function p5 n input pin p5 n output pin wkp n input pin seg n+1 output pin note: * dont care 8.6.4 pin states table 8.16 shows the port 5 pin states in each operating mode. table 8.16 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp 7 / seg 8 to p5 0 / wkp 0 /seg 1 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 159 8.6.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 01 pucr5 n 01 * mos input pull-up off on off note: * dont care n = 7 to 0 8.7 port 6 8.7.1 overview port 6 is an 8-bit i/o port, configured as shown in figure 8.6. p6 /seg p6 /seg p6 /seg p6 /seg p6 /seg p6 /seg p6 /seg p6 /seg 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 port 6 figure 8.6 port 6 pin configuration 160 8.7.2 register configuration and description table 8.17 shows the port 6 register configuration. table 8.17 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ffe3 port data register 6 (pdr6) bit 76543210 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. port control register 6 (pcr6) bit 76543210 pcr6 7 pcr6 6 pcr6 5 pcr6 4 pcr6 3 pcr6 2 pcr6 1 pcr6 0 initial value 00000000 read/write wwwwwwww pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr6 and in pdr6 are valid only when the corresponding pin is designated in bits sgs3 to sgs0 in lpcr as a general i/o pin. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register. all bits are read as 1. 161 port pull-up control register 6 (pucr6) bit 76543210 pucr6 7 pucr6 6 pucr6 5 pucr6 4 pucr6 3 pucr6 2 pucr6 1 pucr6 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr6 controls whether the mos pull-up of each port 6 pin p6 7 Cp6 0 is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 8.7.3 pin functions table 8.18 shows the port 6 pin functions. table 8.18 port 6 pin functions pin pin functions and selection method p6 7 /seg 16 to p6 4 /seg 13 the pin function depends on bit pcr6 n in pcr6 and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 00 ** or 010 * 011 * or 1 *** pcr6n 0 1 * pin function p6n input pin p6n output pin segn+9 output pin p6 3 /seg 12 to p6 0 /seg 9 the pin function depends on bit pcr6 n in pcr6 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) sgs3 to sgs0 00 ** , 010 * or 0110 0111 or 1 *** pcr6n 0 1 * pin function p6n input pin p6n output pin segn+9 output pin note: * dont care 162 8.7.4 pin states table 8.19 shows the port 6 pin states in each operating mode. table 8.19 port 6 pin states pins reset sleep subsleep standby watch subactive active p6 7 /seg 16 to p6 0 /seg 9 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.7.5 mos input pull-up port 6 has a built-in mos input pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 01 puc6 n 01 * mos input pull-up off on off note: * dont care n = 7 to 0 163 8.8 port 7 8.8.1 overview port 7 is an 8-bit i/o port, configured as shown in figure 8.7. p7 /seg p7 /seg p7 /seg p7 /seg p7 /seg p7 /seg p7 /seg p7 /seg 7 6 5 4 3 2 1 0 24 23 22 21 20 19 18 17 port 7 figure 8.7 port 7 pin configuration 8.8.2 register configuration and description table 8.20 shows the port 7 register configuration. table 8.20 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea port data register 7 (pdr7) bit 76543210 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. 164 upon reset, pdr7 is initialized to h'00. port control register 7 (pcr7) bit 76543210 pcr7 7 pcr7 6 pcr7 5 pcr7 4 pcr7 3 pcr7 2 pcr7 1 pcr7 0 initial value 00000000 read/write wwwwwwww pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr7 and in pdr7 are valid only when the corresponding pin is designated in bits sgs3 to sgs0 in lpcr as a general i/o pin. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register. all bits are read as 1. 8.8.3 pin functions table 8.21 shows the port 7 pin functions. table 8.21 port 7 pin functions pin pin functions and selection method p7 7 /seg 24 to p7 4 /seg 21 the pin function depends on bit pcr7 n in pcr7 and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 00 ** 01 ** or 1 *** pcr7n 0 1 * pin function p7n input pin p7n output pin segn+17 output pin p7 3 /seg 20 to p7 0 /seg 17 the pin function depends on bit pcr7 n in pcr7 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) sgs3 to sgs0 00 ** or 0100 0101, 011 * or 1 **** pcr7n 0 1 * pin function p7n input pin p7n output pin segn+17 output pin note: * dont care 165 8.8.4 pin states table 8.22 shows the port 7 pin states in each operating mode. table 8.22 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 /seg 24 to p7 0 /seg 17 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.9 port 8 8.9.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8.9. p8 /seg p8 /seg p8 /seg p8 /seg p8 /seg p8 /seg p8 /seg p8 /seg 7 6 5 4 3 2 1 0 32 31 30 29 28 27 26 25 port 8 figure 8.8 port 8 pin configuration 8.9.2 register configuration and description table 8.23 shows the port 8 register configuration. table 8.23 port 8 registers name abbrev. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb 166 port data register 8 (pdr8) bit 76543210 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. port control register 8 (pcr8) pcr8 7 pcr8 6 pcr8 5 pcr8 4 pcr8 3 pcr8 2 pcr8 1 pcr8 0 initial value 00000000 read/write wwwwwwww pcr8 is an 8-bit register for controlling whether each of the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr8 and in pdr8 are valid only when the corresponding pin is designated in bits sgs3 to sgs0 in lpcr as a general i/o pin. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register. all bits are read as 1. 167 8.9.3 pin functions table 8.24 shows the port 8 pin functions. table 8.24 port 8 pin functions pin pin functions and selection method p8 7 /seg 32 to p8 4 /seg 29 the pin function depends on bit pcr8 n in pcr8 and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 000 * 001 * , 01 ** or 1 *** pcr8n 0 1 * pin function p8n input pin p8n output pin segn+25 output pin p8 3 /seg 28 to p8 0 /seg 25 the pin function depends on bit pcr8 n in pcr8 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) sgs3 to sgs0 000 * or 0010 0011, 01 ** or 1 *** pcr8n 0 1 * pin function p8n input pin p8n output pin segn+25 output pin note: * dont care 8.9.4 pin states table 8.25 shows the port 8 pin states in each operating mode. table 8.25 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 /seg 32 to p8 0 /seg 25 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 168 8.10 port 9 8.10.1 overview port 9 is an 8-bit i/o port configured as shown in figure 8.9. p9 /seg /cl p9 /seg /cl p9 /seg /do p9 /seg /m p9 /seg p9 /seg p9 /seg p9 /seg 7 6 5 4 3 2 1 0 40 39 38 37 36 35 34 33 port 9 1 2 figure 8.9 port 9 pin configuration 8.10.2 register configuration and description table 8.26 shows the port 9 register configuration. table 8.26 port 9 registers name abbrev. r/w initial value address port data register 9 pdr9 r/w h'00 h'ffdc port control register 9 pcr9 w h'00 h'ffec port data register 9 (pdr9) bit 76543210 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr9 is an 8-bit register that stores data for port 9 pins p9 7 to p9 0 . if port 9 is read while pcr9 bits are set to 1, the values stored in pdr9 are read, regardless of the actual pin states. if port 9 is read while pcr9 bits are cleared to 0, the pin states are read. 169 upon reset, pdr9 is initialized to h'00. port control register 9 (pcr9) bit 76543210 pcr9 7 pcr9 6 pcr9 5 pcr9 4 pcr9 3 pcr9 2 pcr9 1 pcr9 0 initial value 00000000 read/write wwwwwwww pcr9 is an 8-bit register for controlling whether each of the port 9 pins p9 7 to p9 0 functions as an input or output pin. setting a pcr9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr9 and in pdr9 are valid only when the corresponding pin is designated in bits sgs3 to sgs0 in lpcr as a general i/o pin. upon reset, pcr9 is initialized to h'00. pcr9 is a write-only register. all bits are read as 1. 8.10.3 pin functions table 8.27 shows the port 9 pin functions. table 8.27 port 9 pin functions pin pin functions and selection method p9 7 /seg 40 /cl 1 the pin function depends on bit pcr9 7 in pcr9, and bits sgx and sgs3 to sgs0 in lpcr. sgs3 to sgs0 0000 not 0000 * sgx 0 0 1 pcr9 7 01 ** pin function p9 7 input pin p9 7 output pin seg 40 output pin cl 1 output pin p9 6 /seg 39 /cl 2 the pin function depends on bit pcr9 6 in pcr9, and bits sgx and sgs3 to sgs0 in lpcr. sgs3 to sgs0 0000 not 0000 * sgx 0 0 1 pcr9 6 01 * * pin function p9 6 input pin p9 6 output pin seg 39 output pin cl 2 output pin note: * dont care 170 table 8.27 port 9 pin functions (cont) pin pin functions and selection method p9 5 /seg 38 /do the pin function depends on bit pcr9 5 in pcr9, and bits sgx and sgs3 to sgs0 in lpcr. sgs3 to sgs0 0000 not 0000 * sgx 0 0 1 pcr9 5 01 * * pin function p9 5 input pin p9 5 output pin seg 38 output pin do output pin p9 4 /seg 37 /m the pin function depends on bit pcr9 4 in pcr9, and bits sgx and sgs3 to sgs0 in lpcr. sgs3 to sgs0 0000 not 0000 * sgx 0 0 1 pcr9 4 01 ** pin function p9 4 input pin p9 4 output pin seg3 7 output pin m output pin 9 3 /seg 36 to p9 0 /seg 33 the pin function depends on bit pcr9 n in pcr9 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) sgs3 to sgs0 0000 not 0000 pcr9 n 01 * pin function p9 n input pin p9 n output pin seg n+33 output pin note: * dont care 171 8.10.4 pin states table 8.28 shows the port 9 pin states in each operating mode. table 8.28 port 9 pin states pins reset sleep subsleep standby watch subactive active p9 7 /seg 40 /cl 1 p9 6 /seg 39 /cl 2 p9 5 /seg 38 /do p9 4 /seg 37 /m p9 3 /seg 36 to p9 0 /seg 33 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.11 port a 8.11.1 overview port a is a 4-bit i/o port, configured as shown in figure 8.10. pa /com pa /com pa /com pa /com 3 2 1 0 port a 4 3 2 1 figure 8.10 port a pin configuration 172 8.11.2 register configuration and description table 8.29 shows the port a register configuration. table 8.29 port a registers name abbrev. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f0 h'ffed port data register a (pdra) bit 76543210 pa 3 pa 2 pa 1 pa 0 initial value 11110000 read/write r/wr/wr/wr/w pdra is an 8-bit register that stores data for port a pins pa 3 to pa 0 . if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0. port control register a (pcra) bit 76543210 pcra 3 pcra 2 pcra 1 pcra 0 initial value 11110000 read/write wwww pcra is an 8-bit register for controlling whether each of the port a pins pa 3 to pa 0 functions as an input or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcra and in pdra are valid only when the corresponding pin is designated in lpcr as a general i/o pin. upon reset, pcra is initialized to h'f0. pcra is a write-only register. all bits are read as 1. 173 8.11.3 pin functions table 8.30 gives the port a pin functions. table 8.30 port a pin functions pin pin functions and selection method pa 3 /com 4 the pin function depends on bit pcra 3 in pcra and bits dts1, dts0, cmx, sgx, and sgs3 to sgs0 in lpcr. cmx * 0 * 01 * dts1, dts0 ** not 11 ** not 11 not 11 11 sgx 0 1 * 01 * 1 * 1 * sgs3 to sgs0 0000 not 0000 0000 not 0000 0000 not 0000 0000 not 0000 pcra 3 01 * pin function pa 3 input pin pa 3 output pin com 4 output pin pa 2 /com 3 the pin function depends on bit pcra 2 in pcra and bits dts1, dts0, cmx, sgx, and sgs3 to sgs0 in lpcr. cmx * 0 * 01 * dts1, dts0 ** 00 or 01 ** 00 or 01 00 or 01 not 00 or 01 sgx 0 1 * 01 * 1 * 1 * sgs3 to sgs0 0000 not 0000 0000 not 0000 0000 not 0000 0000 not 0000 pcra 2 01 * pin function pa 2 input pin pa 2 output pin com 3 output pin pa 1 /com 2 the pin function depends on bit pcra 1 in pcra and bits dts1, dts0, cmx, sgx, and sgs3 to sgs0 in lpcr. cmx * 0 * 01 * dts1, dts0 ** 00 ** 00 00 not 00 sgx 0 1 * 01 * 1 * 1 * sgs3 to sgs0 0000 not 0000 0000 not 0000 0000 not 0000 0000 not 0000 pcra 1 01 * pin function pa 1 input pin pa 1 output pin com 2 output pin note: * dont care 174 table 8.30 port a pin functions (cont) pin pin functions and selection method pa 0 /com 1 the pin function depends on bit pcra0 in pcra, and bits sgx and sgs3 to sgs0 in lpcr. sgs3 to sgs0 0000 0000 not 0000 sgx 0 1 * pcra 0 01 * pin function pa 0 input pin pa 0 output pin com 1 output pin note: * dont care 8.11.4 pin states table 8.31 shows the port a pin states in each operating mode. table 8.31 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 175 8.12 port b 8.12.1 overview port b is an 8-bit input-only port, configured as shown in figure 8.11. pb /an pb /an pb /an pb /an pb /an pb /an pb /an pb /an 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port b figure 8.11 port b pin configuration 8.12.2 register configuration and description table 8.32 shows the port b register configuration. table 8.32 port b register name abbrev. r/w address port data register b pdrb r h'ffde port data register b (pdrb) bit 76543210 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 read/write rrrrrrrr reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. 176 8.13 port c 8.13.1 overview port c is a 4-bit input-only port, configured as shown in figure 8.12. pc /an pc /an pc /an pc /an 3 2 1 0 11 10 9 8 port c figure 8.12 port c pin configuration 8.13.2 register configuration and description table 8.33 shows the port c register configuration. table 8.33 port c register name abbrev. r/w address port data register c pdrc r h'ffdf port data register c (pdrc) bit 76543210 pc3pc2pc1pc0 read/write rrrr reading pdrc always gives the pin states. however, if a port c pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. 177 section 9 timers 9.1 overview the h8/3834 series provides five timers (timers a, b, c, f, and g) on-chip. table 9.1 outlines the functions of timers a, b, c, f, and g. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a 8-bit timer interval timer f /8 to f /8192 (8 choices) 8-bit timer time base f w /128 (choice of 4 overflow periods) 8-bit timer clock output f /4 to f /32, f w /4 to f w /32 (8 choices) tmow timer b 8-bit timer interval timer event counter f /4 to f /8192 (7 choices) tmib timer c 8-bit timer interval timer event counter choice of up- or down- counting f /4 to f /8192, f w /4 (7 choices) tmic counting direction can be controlled by software or hardware timer f 16-bit timer event counter can be used as two independent 8-bit timers output compare f /2 to f /32 (4 choices) tmif tmofl tmofh timer g 8-bit timer input capture interval timer f /2 to f /64, f w /2 (4 choices) tmig counter clear designation possible built-in noise canceller circuit for input capture 178 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768-khz crystal oscillator is connected. a clock signal divided from 32.768 khz or from the system clock can be output at the tmow pin. features features of timer a are given below. choice of eight internal clock sources ( f /8192, f /4096, f /2048, f /512, f /256, f /128, f /32, f /8). choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). an interrupt is requested when the counter overflows. any of eight clock signals can be output from pin tmow: 32.768 khz divided by 32, 16, 8, or 4 (1 khz, 2 khz, 4 khz, 8 khz), or the system clock divided by 32, 16, 8, or 4. 179 block diagram figure 9.1 shows a block diagram of timer a. f f f f f f f f psw internal data bus pss tmow 1/4 tma tca /32 /16 /8 /4 w w w w f f f f /32 /16 /8 /4 w w w w /128 w f f f ff ff f /8192, /4096, /2048, /512, /256, /128, /32, /8 irrta ? 8 ? 64 ? 128 ? 256 * * * * /4 w notation: tma: tca: irrta: psw: pss: f note: can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s w figure 9.1 block diagram of timer a pin configuration table 9.2 shows the timer a pin configuration. table 9.2 pin configuration name abbrev. i/o function clock output tmow output output of waveform generated by timer a output circuit 180 register configuration table 9.3 shows the register configuration of timer a. table 9.3 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'10 h'ffb0 timer counter a tca r h'00 h'ffb1 9.2.2 register descriptions timer mode register a (tma) bit 76543210 tma7 tma6 tma5 tma3 tma2 tma1 tma0 initial value 00010000 read/write r/w r/w r/w r/w r/w r/w r/w tma is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. upon reset, tma is initialized to h'10. bits 7 to 5clock output select (tma7 to tma5): bits 7 to 5 choose which of eight clock signals is output at the tmow pin. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. bit 7: tma7 bit 6: tma6 bit 5: tma5 clock output 000 f /32 (initial value) 1 f /16 10 f /8 1 f /4 100 f w /32 1 f w /16 10 f w /8 1 f w /4 bit 4reserved bit: bit 4 is reserved; it is always read as 1, and cannot be modified. 181 bits 3 to 0internal clock select (tma3 to tma0): bits 3 to 0 select the clock input to tca. description bit 3: tma3 bit 2: tma2 bit 1: tma1 bit 0: tma0 prescaler and divider ratio or overflow period function 0000 pss, f /8192 (initial value) interval timer 1 pss, f /4096 1 0 pss, f /2048 1 pss, f /512 1 0 0 pss, f /256 1 pss, f /128 1 0 pss, f /32 1 pss, f /8 1000 psw, 1 s clock time base 1 psw, 0.5 s 1 0 psw, 0.25 s 1 psw, 0.03125 s 1 0 0 psw and tca are reset 1 10 1 timer counter a (tca) bit 76543210 tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 initial value 00000000 read/write rrrrrrrr tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 182 9.2.3 timer operation interval timer operation: when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.3, interrupts. real-time clock time base operation: when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. clock output: setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. eight different clock output signals can be selected by means of bits tma7 to tma5 in tma. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 183 9.2.4 timer a operation states table 9.4 summarizes the timer a operation states. table 9.4 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby tca interval reset functions functions halted halted halted halted clock time base reset functions functions functions functions functions halted tma reset functions retained retained functions retained retained note: when real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ f (s) in the count cycle. 9.3 timer b 9.3.1 overview timer b is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. features features of timer b are given below. choice of seven internal clock sources ( f /8192, f /2048, f /512, f /256, f /64, f /16, f /4) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. block diagram figure 9.2 shows a block diagram of timer b. 184 pss tmb tcb tlb f tmib irrtb notation: tmb: tcb: tlb: irrtb: pss: timer mode register b timer counter b timer load register b timer b overflow interrupt request flag prescaler s internal data bus figure 9.2 block diagram of timer b pin configuration table 9.5 shows the timer b pin configuration. table 9.5 pin configuration name abbrev. i/o function timer b event input tmib input event input to tcb register configuration table 9.6 shows the register configuration of timer b. table 9.6 timer b registers name abbrev. r/w initial value address timer mode register b tmb r/w h'78 h'ffb2 timer counter b tcb r h'00 h'ffb3 timer load register b tlb w h'00 h'ffb3 185 9.3.2 register descriptions timer mode register b (tmb) bit 76543210 tmb7 tmb2 tmb1 tmb0 initial value 01111000 read/write r/w r/wr/wr/w tmb is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmb is initialized to h'78. bit 7auto-reload function select (tmb7): bit 7 selects whether timer b is used as an interval timer or auto-reload timer. bit 7: tmb7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 to 3reserved bits: bits 6 to 3 are reserved; they always read 1, and cannot be modified. bits 2 to 0clock select (tmb2 to tmb0): bits 2 to 0 select the clock input to tcb. for external event counting, either the rising or falling edge can be selected. bit 2: tmb2 bit 1: tmb1 bit 0: tmb0 description 0 0 0 internal clock: f /8192 (initial value) 1 internal clock: f /2048 1 0 internal clock: f /512 1 internal clock: f /256 1 0 0 internal clock: f /64 1 internal clock: f /16 1 0 internal clock: f /4 1 external event (tmib): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the irq edge select register (iegr). see 3.3.2, interrupt control registers, for details on the irq edge select register. be sure to set bit irq1 in port mode register 1 (pmr1) to 1 before setting bits tmb2 to tmb0 to 111. 186 timer counter b (tcb) bit 76543210 tcb7 tcb6 tcb5 tcb4 tcb3 tcb2 tcb1 tcb0 initial value 00000000 read/write rrrrrrrr tcb is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmb2 to tmb0 in timer mode register b (tmb). tcb values can be read by the cpu at any time. when tcb overflows from h'ff to h'00 or to the value set in tlb, the irrtb bit in interrupt request register 2 (irr2) is set to 1. tcb is allocated to the same address as timer load register b (tlb). upon reset, tcb is initialized to h'00. timer load register b (tlb) bit 76543210 tlb7 tlb6 tlb5 tlb4 tlb3 tlb2 tlb1 tlb0 initial value 00000000 read/write wwwwwwww tlb is an 8-bit write-only register for setting the reload value of timer counter b. when a reload value is set in tlb, the same value is loaded into timer counter b (tcb) as well, and tcb starts counting up from that value. when tcb overflows during operation in auto-reload mode, the tlb value is loaded into tcb. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlb as to tcb. upon reset, tlb is initialized to h'00. 187 9.3.3 timer operation interval timer operation: when bit tmb7 in timer mode register b (tmb) is cleared to 0, timer b functions as an 8-bit interval timer. upon reset, tcb is cleared to h'00 and bit tmb7 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer b is selected from seven internal clock signals output by prescaler s, or an external clock input at pin tmib. the selection is made by bits tmb2 to tmb0 of tmb. after the count value in tcb reaches h'ff, the next clock signal input causes timer b to overflow, setting bit irrtb to 1 in interrupt request register 2 (irr2). if ientb = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tcb returns to h'00 and starts counting up again. during interval timer operation (tmb7 = 0), when a value is set in timer load register b (tlb), the same value is set in tcb. note: * for details on interrupts, see 3.3, interrupts. auto-reload timer operation: setting bit tmb7 in tmb to 1 causes timer b to function as an 8-bit auto-reload timer. when a reload value is set in tlb, the same value is loaded into tcb, becoming the value from which tcb starts its count. after the count value in tcb reaches h'ff, the next clock signal input causes timer b to overflow. the tlb value is then loaded into tcb, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmb7 = 1), when a new value is set in tlb, the tlb value is also set in tcb. event counter operation: timer b can operate as an event counter, counting rising or falling edges of an external event signal input at pin tmib. external event counting is selected by setting bits tmb2 to tmb0 in timer mode register b to all 1s (111). when timer b is used to count external event input, bit irq1 in port mode register 1 (pmr1) should be set to 1, and bit ien1 in interrupt enable register 1 (ienr1) should be cleared to 0 to disable irq 1 interrupt requests. 188 9.3.4 timer b operation states table 9.7 summarizes the timer b operation states. table 9.7 timer b operation states operation mode reset active sleep watch sub- active sub- sleep standby tcb interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tmb reset functions retained retained retained retained retained 9.4 timer c 9.4.1 overview timer c is an 8-bit timer that increments or decrements each time a clock pulse is input. this timer has two operation modes, interval and auto reload. features the main features of timer c are given below. choice of seven internal clock sources ( f /8192, f /2048, f /512, f /64, f /16, f /4, f w /4) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. can be switched between up- and down-counting by software or hardware. when f w /4 is selected as the internal clock source, or when an external clock is selected, timer c can function in subactive mode and subsleep mode. 189 block diagram figure 9.3 shows a block diagram of timer c. notation: tmc: tcc: tlc: irrtc: pss: timer mode register c timer counter c timer load register c timer c overflow interrupt request flag prescaler s ud pss tmic w /4 tmc tcc tlc irrtc internal data bus f f figure 9.3 block diagram of timer c pin configuration table 9.8 shows the timer c pin configuration. table 9.8 pin configuration name abbrev. i/o function timer c event input tmic input event input to tcc timer c up/down control ud input selection of counting direction register configuration table 9.9 shows the register configuration of timer c. 190 table 9.9 timer c registers name abbrev. r/w initial value address timer mode register c tmc r/w h'18 h'ffb4 timer counter c tcc r h'00 h'ffb5 timer load register c tlc w h'00 h'ffb5 9.4.2 register descriptions timer mode register c (tmc) bit 76543210 tmc7 tmc6 tmc5 tmc2 tmc1 tmc0 initial value 00011000 read/write r/w r/w r/w r/w r/w r/w tmc is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. upon reset, tmc is initialized to h'18. bit 7auto-reload function select (tmc7): bit 7 selects whether timer c is used as an interval timer or auto-reload timer. bit 7: tmc7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 and 5counter up/down control (tmc6 and tmc5): these bits select the counting direction of timer counter c (tcc), or allow hardware to control the counting direction using pin ud. bit 6: tmc6 bit 5: tmc5 description 0 0 tcc is an up-counter (initial value) 1 tcc is a down-counter 1 * tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up- counter if the ud input is low. note: * dont care 191 bits 4 and 3reserved bits: bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. bits 2 to 0clock select (tmc2 to tmc0): bits 2 to 0 select the clock input to tcc. for external clock counting, either the rising or falling edge can be selected. bit 2: tmc2 bit 1: tmc1 bit 0: tmc0 description 0 0 0 internal clock: f /8192 (initial value) 1 internal clock: f /2048 1 0 internal clock: f /512 1 internal clock: f /64 1 0 0 internal clock: f /16 1 internal clock: f /4 1 0 internal clock: f w /4 1 external event (tmic): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg2 in the irq edge select register (iegr). see 3.3.2, for details on the irq edge select register. be sure to set bit irq2 in port mode register 1 (pmr1) to 1 before setting bits tmc2 to tmc0 to 111. timer counter c (tcc) bit 76543210 tcc7 tcc6 tcc5 tcc4 tcc3 tcc2 tcc1 tcc0 initial value 00000000 read/write rrrrrrrr tcc is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). tcc values can be read by the cpu at any time. when tcc overflows (from h'ff to h'00 or to the value set in tlc) or underflows (from h'00 to h'ff or to the value set in tlc), the irrtc bit in interrupt request register 2 (irr2) is set to 1. tcc is allocated to the same address as timer load register c (tlc). upon reset, tcc is initialized to h'00. 192 timer load register c (tlc) bit 76543210 tlc7 tlc6 tlc5 tlc4 tlc3 tlc2 tlc1 tlc0 initial value 00000000 read/write rrrrrrrr tlc is an 8-bit write-only register for setting the reload value of tcc. when a reload value is set in tlc, the same value is loaded into timer counter c (tcc) as well, and tcc starts counting up or down from that value. when tcc overflows or underflows during operation in auto-reload mode, the tlc value is loaded into tcc. accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00. 9.4.3 timer operation interval timer operation: when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, timer counter c (tcc) is initialized to h'00 and tmc to h'18. after a reset, the counter continues uninterrupted incrementing as an interval up-counter. the clock input to timer c is selected from seven internal clock signals output by prescalers s and w, or an external clock input at pin tmic. the selection is made by bits tmc2 to tmc0 in tmc. either software or hardware can control whether tcc counts up or down. the selection is made by tmc bits tmc6 and tmc5. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (underflow), setting bit irrtc to 1 in interrupt request register 2 (irr2). if ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested. at overflow or underflow, tcc returns to h'00 or h'ff and starts counting up or down again. during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: * for details on interrupts, see 3.3, interrupts. 193 auto-reload timer operation: setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (underflow). the tlc value is then loaded tcc, and the count continues from that value. the overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmc7 = 1), when a new value is set in tlc, the tlc value is also set in tcc. event counter operation: timer c can operate as an event counter, counting an event signal input at pin tmic. external event counting is selected by setting tmc bits tmc2 to tmc0 to all 1s (111). tcc counts up or down at the rising or falling edge of the input at pin tmic. when timer c is used to count external event inputs, bit irq2 in port mode register 1 (pmr1) should be set to 1, and bit ien2 in interrupt enable register 1 (ienr1) should be cleared to 0 to disable irq2 interrupt requests. tcc up/down control by hardware: the counting direction of timer c can be controlled by input at pin ud. when bit tmc6 in tmc is set to 1, high-level input at the ud pin selects down- counting, while low-level input selects up-counting. when using input at pin ud for this control function, set the ud bit in port mode register 2 (pmr2) to 1. 194 9.4.4 timer c operation states table 9.10 summarizes the timer c operation states. table 9.10 timer c operation states operation mode reset active sleep watch sub- active sub- sleep standby tcc interval reset functions functions halted functions/ halted * functions/ halted * halted tcc auto reload reset functions functions halted functions/ halted * functions/ halted * halted tmc reset functions retained retained functions retained retained note: when f w /4 is selected as the internal clock of tcc in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ f (s) in the count cycle. * when timer c is operated in subactive mode or subsleep mode, either an external clock or the f w /4 internal clock must be selected. the counter will not operate in these modes if another clock is selected. if the internal f w /4 clock is selected when f w /8 is being used as the subclock f sub , the lower 2 bits of the counter will operate on the same cycle, with the least significant bit not being counted. 9.5 timer f 9.5.1 overview timer f is a 16-bit timer with an output compare function. compare match signals can be used to reset the counter, request an interrupt, or toggle the output. timer f can also be used for external event counting, and can operate as two independent 8-bit timers, timer fh and timer fl. features features of timer f are given below. choice of four internal clock sources ( f /32, f /16, f /4, f /2) or an external clock (can be used as an external event counter). output from pin tmofh is toggled by one compare match signal (the initial value of the toggle output can be set). counter can be reset by the compare match signal. two interrupt sources: counter overflow and compare match. can operate as two independent 8-bit timers (timer fh and timer fl) in 8-bit mode. 195 timer fh 8-bit timer (clocked by timer fl overflow signals when timer f operates as a 16-bit timer). choice of four internal clocks ( f /32, f /16, f /4, f /2). output from pin tmofh is toggled by one compare match signal (the initial value of the toggle output can be set). counter can be reset by the compare match signal. two interrupt sources: counter overflow and compare match. timer fl 8-bit timer/event counter choice of four internal clocks ( f /32, f /16, f /4, f /2) or event input at pin tmif. output from pin tmofl is toggled by one compare match signal (the initial value of the toggle output can be set). counter can be reset by the compare match signal. two interrupt sources: counter overflow and compare match. 196 block diagram figure 9.4 shows a block diagram of timer f. f pss internal data bus compare circuit ocrfh toggle circuit toggle circuit match notation: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: irrtfh: irrtfl: pss: timer control register f timer control status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl timer fh interrupt request flag timer fl interrupt request flag prescaler s irrtfh irrtfl tmif tmofl tmofh tcfl tcrf ocrfl tcfh compare circuit tcsrf figure 9.4 block diagram of timer f 197 pin configuration table 9.11 shows the timer f pin configuration. table 9.11 pin configuration name abbrev. i/o function timer f event input tmif input event input to tcfl timer fh output tmofh output timer fh toggle output timer fl output tmofl output timer fl toggle output register configuration: table 9.12 shows the register configuration of timer f. table 9.12 timer f registers name abbrev. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb 9.5.2 register descriptions 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) tcf bit 1514131211109876543210 initial value 0000000000000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcfh tcfl 198 tcf is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, tcfh and tcfl. tcf can be used as a 16-bit counter, with tcfh as the upper 8 bits and tcfl as the lower 8 bits of the counter, or tcfh and tcfl can be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but in 16-bit mode, data transfer with the cpu takes place via a temporary register (temp). for details see 9.5.3, interface with the cpu. upon reset, tcfh and tcfl are each initialized to h'00. 16-bit mode (tcf) 16-bit mode is selected by clearing bit cksh2 to 0 in timer control register f (tcrf). the tcf input clock is selected by tcrf bits cksl2 to cksl0. timer control status register f (tcsrf) can be set so that counter tcf will be cleared by compare match. when tcf overflows from h'ffff to h'0000, the overflow flag (ovfh) in tcsrf is set to 1. if bit ovieh in tcsrf is set to 1 when an overflow occurs, bit irrtfh in interrupt request register 2 (irr2) will be set to 1; and if bit ientfh in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt will be requested. 8-bit mode (tcfh, tcfl) when bit cksh2 in timer control register f (tcrf) is set to 1, timer f functions as two separate 8-bit counters, tcfh and tcfl. the tcfh (tcfl) input clock is selected by tcrf bits cksh2 to cksh0 (cksl2 to cksl0). tcfh (tcfl) can be cleared by a compare match signal. this designation is made in bit cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, the overflow flag ovfh (ovfl) in tcsrf is set to 1. if bit ovieh (oviel) in tcsrf is set to 1 when an overflow occurs, bit irrtfh (irrthl) in interrupt request register 2 (irr2) will be set to 1; and if bit ientfh (ientfl) in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt will be requested. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) ocrf bit 1514131211109876543210 initial value 1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocrfh ocrfl 199 ocrf is a 16-bit read/write output compare register consisting of two 8-bit read/write registers ocrfh and ocrfl. it can be used as a 16-bit output compare register, with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits of the register, or ocrfh and ocrfl can be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but in 16-bit mode, data transfer with the cpu takes place via a temporary register (temp). for details see 9.5.3, interface with the cpu. upon reset, ocrfh and ocrfl are each initialized to h'ff. 16-bit mode (ocrf) 16-bit mode is selected by clearing bit cksh2 to 0 in timer control register f (tcrf). the ocrf contents are always compared with the 16-bit timer counter (tcf). when the contents match, the compare match flag (cmfh) in tcsrf is set to 1. also, irrtfh in interrupt request register 2 (irr2) is set to 1. if bit ientfh in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. output for pin tmofh can be toggled by compare match. the output level can also be set to high or low by bit tolh of timer control register f (tcrf). 8-bit mode (ocrfh, ocrfl) setting bit cksh2 in tcrf to 1 results in two 8-bit registers, ocrfh and ocrfl. the ocrfh contents are always compared with tcfh, and the ocrfl contents are always compared with tcfl. when the contents match, the compare match flag (cmfh or cmfl) in tcsrf is set to 1. also, bit irrtfh (irrtfl) in interrupt request register 2 (irr2) set to 1. if bit ientfh (ientfl) in interrupt enable register 2 (ienr2) is set to 1 at this time, a cpu interrupt is requested. the output at pin tmofh (tmofl) can be toggled by compare match. the output level can also be set to high or low by bit tolh (toll) of the timer control register (tcrf). timer control register f (tcrf) bit 76543210 tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 initial value 00000000 read/write wwwwwwww tcrf is an 8-bit write-only register. it is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external clock, and to select the output level at pins tmofh and tmofl. upon reset, tcrf is initialized to h'00. 200 bit 7toggle output level h (tolh): bit 7 sets the output level at pin tmofh. the setting goes into effect immediately after this bit is written. bit 7: tolh description 0 low level (initial value) 1 high level bits 6 to 4clock select h (cksh2 to cksh0): bits 6 to 4 select the input to tcfh from four internal clock signals or the overflow of tcfl. bit 6: cksh2 bit 5: cksh1 bit 4: cksh0 description 0 ** 16-bit mode selected. tcfl overflow signals are counted (initial value) 1 0 0 internal clock: f /32 1 internal clock: f /16 1 0 internal clock: f /4 1 internal clock: f /2 note: * dont care bit 3toggle output level l (toll): bit 3 sets the output level at pin tmofl. the setting goes into effect immediately after this bit is written. bit 3: toll description 0 low level (initial value) 1 high level bits 2 to 0clock select l (cksl2 to cksl0): bits 2 to 0 select the input to tcfl from four internal clock signals or external event input. 201 bit 2: cksl2 bit 1: cksl1 bit 0: cksl0 description 0 ** external event (tmif). rising or falling edge is counted * 1 (initial value) 1 0 0 internal clock: f /32 1 internal clock: f /16 1 0 internal clock: f /4 1 internal clock: f /2 note: 1. the edge of the external event signal is selected by bit ieg3 in the irq edge select register (iegr). see 3.3.2, for details on the irq edge select register. note that switching the tmif pin function by changing bit irq3 in port mode register 1 (pmr1) from 0 to 1 or from 1 to 0 while the tmif pin is at the low level may cause the timer f counter to be incremented. * dont care timer control/status register f (tcsrf) bit 76543210 ovfh cmfh ovieh cclrh ofl cmfl oviel cclrl initial value 00000000 read/write r/w * r/w * r/w r/w r/w * r/w * r/w r/w note: * only 0 can be written, to clear flag. tcsrf is an 8-bit read/write register. it is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. upon reset, tcsrf is initialized to h'00. bit 7timer overflow flag h (ovfh): bit 7 is a status flag indicating tcfh overflow (h'ff to h'00). this flag is set by hardware and cleared by software. it cannot be set by software. bit 7: ovfh description 0 clearing conditions: after reading ovfh = 1, cleared by writing 0 to ovfh (initial value) 1 setting conditions: set when the value of tcfh goes from h'ff to h'00 bit 6compare match flag h (cmfh): bit 6 is a status flag indicating a compare match between tcfh and ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. 202 bit 6: cmfh description 0 clearing conditions: after reading cmfh = 1, cleared by writing 0 to cmfh (initial value) 1 setting conditions: set when the tcfh value matches ocrfh value bit 5timer overflow interrupt enable h (ovieh): bit 5 enables or disables tcfh overflow interrupts. bit 5: ovieh description 0 tcfh overflow interrupt disabled (initial value) 1 tcfh overflow interrupt enabled bit 4counter clear h (cclrh): in 16-bit mode, bit 4 selects whether or not tcf is cleared when a compare match occurs between tcf and ocrf. in 8-bit mode, bit 4 selects whether or not tcfh is cleared when a compare match occurs between tcfh and ocrfh. bit 4: cclrh description 0 16-bit mode: tcf clearing by compare match disabled (initial value) 8-bit mode: tcfh clearing by compare match disabled 1 16-bit mode: tcf clearing by compare match enabled 8-bit mode: tcfh clearing by compare match enabled bit 3timer overflow flag l (ovfl): bit 3 is a status flag indicating tcfl overflow (h'ff to h'00). this flag is set by hardware and cleared by software. it cannot be set by software. bit 3: ovfl description 0 clearing conditions: after reading ovfl = 1, cleared by writing 0 to ovfl (initial value) 1 setting conditions: set when the value of tcfl goes from h'ff to h'00 bit 2compare match flag l (cmfl): bit 2 is a status flag indicating a compare match between tcfl and ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. 203 bit 2: cmfl description 0 clearing conditions: after reading cmfl = 1, cleared by writing 0 to cmfl (initial value) 1 setting conditions: set when the tcfl value matches the ocrfl value bit 1timer overflow interrupt enable l (oviel): bit 1 enables or disables tcfl overflow interrupts. bit 1: oviel description 0 tcfl overflow interrupt disabled (initial value) 1 tcfl overflow interrupt enabled bit 0counter clear l (cclrl): bit 0 selects whether or not tcfl is cleared when a compare match occurs between tcfl and ocrfl. bit 0: cclrl description 0 tcfl clearing by compare match disabled (initial value) 1 tcfl clearing by compare match enabled 9.5.3 interface with the cpu tcf and ocrf are 16-bit read/write registers, whereas the data bus between the cpu and on-chip peripheral modules has an 8-bit width. for this reason, when the cpu accesses tcf or ocrf, it makes use of an 8-bit temporary register (temp). in 16-bit mode, when reading or writing tcf or writing ocrf, always use two consecutive byte size mov instructions, and always access the upper byte first. data will not be transferred properly if only the upper byte or only the lower byte is accessed. in 8-bit mode there is no such restriction on the order of access. write access: when the upper byte is written, the upper-byte data is loaded into the temp register. next when the lower byte is written, the data in temp goes to the upper byte of the register, and the lower-byte data goes directly to the lower byte of the register. figure 9.5 shows a tcf write operation when h'aa55 is written to tcf. 204 bus interface cpu (h'aa) temp (h'aa) tcfh ( ) tcfl ( ) internal data bus upper byte write bus interface cpu (h'55) temp (h'aa) tcfh (h'aa) tcfl (h'55) internal data bus lower byte write figure 9.5 tcf write operation (cpu ? tcf) read access: when the upper byte of tcf is read, the upper-byte data is sent directly to the cpu, and the lower byte is loaded into temp. next when the lower byte is read, the lower byte in temp is sent to the cpu. when the upper byte of ocrf is read, the upper-byte data is sent directly to the cpu. next when the lower byte is read, the lower-byte data is sent directly to the cpu. 205 figure 9.6 shows a tcf read operation when h'aaff is read from tcf. cpu (h'aa) temp (h'ff) tcfh (h'aa) tcfl (h'ff) internal data bus upper byte read bus interface bus interface cpu (h'ff) temp (h'ff) tcfh (ab) * tcfl (00) * internal data bus lower byte read note: * becomes h'ab00 if counter is incremented once. figure 9.6 tcf read operation (tcf ? cpu) 206 9.5.4 timer operation timer f is a 16-bit timer/counter that increments with each input clock. the value set in output compare register f is constantly compared with the value of timer counter f, and when they match the counter can be cleared, an interrupt can be requested, and the port output can be toggled. timer f can also be used as two independent 8-bit timers. timer f operation: timer f can operate in either 16-bit timer mode or 8-bit timer mode. these modes are described below. 16-bit timer mode timer f operates in 16-bit timer mode when the cksh2 bit in timer control register f (tcrf) is cleared to 0. a reset initializes timer counter f (tcf) to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control status register f (tcsrf) to h'00. timer f begins counting external event input signals (tmif). the edge of the external event signal is selected by the ieg3 bit in the irq edge select register (iegr). any of four internal clocks output by prescaler s, or an external clock, can be selected as the timer f operating clock by bits cksl2 to cksl0 in tcrf. tcf is continuously compared with the contents of ocrf. when these two values match, the cmfh bit in tcsrf is set to 1. at this time if ientfh of ienr2 is 1, a cpu interrupt is requested and the output at pin tmofh is toggled. if the cclrh bit in tcsrf is 1, timer f is cleared. the output at pin tmofh can also be set by the tolh bit in tcrf. if timer f overflows (from h'ffff to h'0000), the ovfh bit in tcsrf is set. at this time, if the ovieh bit in tcsrf and the ientfh bit in ienr2 are both 1, a cpu interrupt is requested. 8-bit timer mode when the cksh2 bit in tcrf is set to 1, timer f operates as two independent 8-bit timers, tcfh and tcfl. the input clock of tcfh/tcfl is selected by bits cksh2 to cksh0/cksl2 to cksl0 in tcrf. when tcfh/tcfl and the contents of ocrfh/ocrfl match, the cmfh/cmfl bit in tcsrf is set to 1. if the ientfh/ientfl bit in ienr2 is 1, a cpu interrupt is requested and the output at pin tmofh/tmofl is toggled. if the cclrh/cclrl bit in tcrf is 1, tcfh/tcfl is cleared. the output at pin tmofh/tmofl can also be set by the tolh/toll bit in tcrf. when tcfh/tcfl overflows from h'ff to h'00, the ovfh/ovfl bit in tcsrf is set to 1. at this time, if the ovieh/oviel bit in tcsrf and the ientfh/ientfl bit in ienr2 are both 1, a cpu interrupt is requested. 207 tcf count timing: tcf is incremented by each pulse of the input clock (internal or external clock). internal clock the settings of bits cksh2 to cksh0 or bits cksl2 to cksl0 in tcrf select one of four internal clock signals divided from the system clock ( f ), namely, f /32, f /16, f /4, or f /2. external clock external clock input is selected by clearing bit cksl2 to 0 in tcrf. either rising or falling edges of the clock input can be counted. the edge of an external event is selected by bit ieg3 in the interrupt controllers iegr register. an external event pulse width of at least two system clock ( f ) cycles is necessary for correct operation of the counter. tmofh and tmofl output timing: the outputs at pins tmofh and tmofl are the values set in bits tolh and toll in tcrf. when a compare match occurs, the output value is inverted. figure 9.7 shows the output timing. tmif (when ieg3 = 1) count input clock tcf ocrf compare match signal tmofh, tmofl n n + 1 n n + 1 nn figure 9.7 tmofh, tmofl output timing tcf clear timing: tcf can be cleared at compare match with ocrf. timer overflow flag (ovf) set timing: ovf is set to 1 when tcf overflows (goes from h'ffff to h'0000). 208 compare match flag set timing: the compare match flags (cmfh or cmfl) are set to 1 when a compare match occurs between tcf and ocrf. a compare match signal is generated in the final state in which the values match (when tcf changes from the matching count value to the next value). when tcf and ocrf match, a compare match signal is not generated until the next counter clock pulse. timer f operation states: table 9.13 summarizes the timer f operation states. table 9.13 timer f operation states operation mode reset active sleep watch sub- active sub- sleep standby tcf reset functions functions halted halted halted halted ocrf reset functions retained retained retained retained retained tcrf reset functions retained retained retained retained retained tcsrf reset functions retained retained retained retained retained 9.5.5 application notes the following conflicts can arise in timer f operation. 16-bit timer mode the output at pin tmofh toggles when all 16 bits match and a compare match signal is generated. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit tolh will be output at pin tmofh. the tmofl output in 16-bit mode is indeterminate, so this output should not be used. use the pin as a general input or output port. if an ocrfl write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfl clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated; bit cmfl is set when the setting conditions are met for the lower 8 bits. the overflow flag (ovfh) is set when tcf overflows; bit ovfl is set if the setting conditions are met when the lower 8 bits overflow. if a write to tcfl occurs at the same time as an overflow signal, the overflow signal is not output. 209 8-bit timer mode ? tcfh and ocrfh the output at pin tmofh toggles when there is a compare match. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit tolh will be output at pin tmofh. if an ocrfh write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write occurs at the same time as an overflow signal, the overflow signal is not output. ? tcfl and ocrfl the output at pin tmofl toggles when there is a compare match. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit toll will be output at pin tmofl. if an ocrfl write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfl clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. if a tcfl write occurs at the same time as an overflow signal, the overflow signal is not output. 210 9.6 timer g 9.6.1 overview timer g is an 8-bit timer, with input capture functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). timer g has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle. when timer g is not used for input capture, it functions as an 8-bit interval timer. features features of timer g are given below. choice of four internal clock sources ( f /64, f /32, f /2, f w /2) input capture function separate input capture registers are provided for the rising and falling edges. counter overflow detection can detect whether overflow occurred when the input capture signal was high or low. choice of counter clear triggers the counter can be cleared at the rising edge, falling edge, or both edges of the input capture signal. two interrupt sources interrupts can be requested by input capture and by overflow. for input capture, the rising or falling edge can be selected. built-in noise-canceller circuit the noise canceller circuit can eliminate high-frequency noise in the input capture signal. operates in subactive and subsleep modes when f w /2 is selected as the internal clock source, timer g can operate in the subactive and subsleep modes. 211 block diagram figure 9.8 shows a block diagram of timer g. pss tmg icrgf tcg icrgr irrtg f f internal data bus level sense circuit noise canceller circuit edge sense circuit w /2 tmig ncs notation: tmg: tcg: icrgf: icrgr: irrtg: ncs: pss: timer mode register g timer counter g input capture register gf input capture register gr timer g interrupt request flag noise canceller select prescaler s figure 9.8 block diagram of timer g pin configuration table 9.14 shows the timer g pin configuration. table 9.14 pin configuration name abbrev. i/o function timer g capture input tmig input timer g capture input 212 register configuration table 9.15 shows the register configuration of timer g. table 9.15 timer g registers name abbrev. r/w initial value address timer mode register g tmg r/w h'00 h'ffbc timer counter g tcg h'00 input capture register gf icrgf r h'00 h'ffbd input capture register gr icrgr r h'00 h'ffbe 9.6.2 register descriptions timer counter g (tcg) bit 76543210 tcg7 tcg6 tcg5 tcg4 tcg3 tcg2 tcg1 tcg0 initial value 00000000 read/write timer counter g (tcg) is an 8-bit up-counter which is incremented by an input clock. the input clock signal is selected by bits cks1 and cks0 in timer mode register g (tmg). to use tcg as an input capture timer, set bit tmig to 1 in pmr1; to use tcg as an interval timer, clear bit tmig to 0.* when tcg is used as an input capture timer, the tcg value can be cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on settings in tmg. when tcg overflows (goes from h'ff to h'00), if the timer overflow interrupt enable bit (ovie) is set to 1 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. tcg cannot be read or written by the cpu. upon reset, tcg is initialized to h'00. note: * an input capture signal may be generated when tmig is rewritten. 213 input capture register gf (icrgf) bit 76543210 icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgf0 initial value 00000000 read/write rrrrrrrr icrgf is an 8-bit read-only register. when the falling edge of the input capture signal is detected, the tcg value at that time is transferred to icrgf. if the input capture interrupt select bit (iiegs) is set to 1 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. to ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2 f or 2 f sub . upon reset, icrgf is initialized to h'00. input capture register gr (icrgr) bit 76543210 icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgr0 initial value 00000000 read/write rrrrrrrr icrgr is an 8-bit read-only register. when the rising edge of the input capture signal is detected, the tcg value at that time is sent to icrgr. if the iiegs bit is cleared to 0 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. to ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2 f or 2 f sub . upon reset, icrgr is initialized to h'00. 214 timer bode register g (tmg) bit 76543210 ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 initial value 00000000 read/write r/w * r/w * r/w r/w r/w r/w r/w r/w note: * only 0 can be written, to clear flag. tmg is an 8-bit read/write register. it controls the choice of four input clocks, counter clear selection, and edge selection for input capture interrupt requests. it also indicates overflow status and enables or disables overflow interrupt requests. upon reset, tmg is initialized to h'00. bit 7timer overflow flag h (ovfh): bit 7 is a status flag indicating that tcg overflowed (from h'ff to h'00) when the input capture signal was high. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7: ovfh description 0 clearing conditions: after reading ovfh = 1, cleared by writing 0 to ovfh (initial value) 1 setting conditions: set when the value of tcg overflows from h'ff to h'00 bit 6timer overflow flag l (ovfl): bit 6 is a status flag indicating that tcg overflowed (from h'ff to h'00) when the input capture signal was low, or in interval timer operation. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6: ovfl description 0 clearing conditions: after reading ovfl = 1, cleared by writing 0 to ovfl (initial value) 1 setting conditions: set when the value of tcg overflows from h'ff to h'00 bit 5timer overflow interrupt enable (ovie): bit 5 enables or disables tcg overflow interrupts. bit 5: ovie description 0 tcg overflow interrupt disabled (initial value) 1 tcg overflow interrupt enabled 215 bit 4input capture interrupt edge select (iiegs): bit 4 selects the input signal edge at which input capture interrupts are requested. bit 4: iiegs description 0 interrupts are requested at the rising edge of the input capture signal (initial value) 1 interrupts are requested at the falling edge of the input capture signal bits 3, 2counter clear 1, 0 (cclr1, cclr0): bits 3 and 2 designate whether tcg is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared. bit 3: cclr1 bit 2: cclr0 description 0 0 tcg is not cleared (initial value) 1 tcg is cleared at the falling edge of the input capture signal 1 0 tcg is cleared at the rising edge of the input capture signal 1 tcg is cleared at both edges of the input capture signal bits 1, 0clock select (cks1, cks0): bits 1 and 0 select the clock input to tcg from four internal clock signals. bit 1: cks1 bit 0: cks0 description 0 0 internal clock: f /64 (initial value) 1 internal clock: f /32 1 0 internal clock: f /2 1 internal clock: f w /2 9.6.3 noise canceller circuit the noise canceller circuit built into the h8/3834 series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. the noise canceller circuit is enabled by the noise canceller select (ncs)* bit in port mode register 2 (pmr2). figure 9.9 shows a block diagram of the noise canceller circuit. 216 input capture signal sampling clock match detection circuit noise canceller output t: selected by bits cks1, cks0. sampling clock c latch d q c latch d q c latch d q c latch d q c latch d q d t d figure 9.9 block diagram of noise canceller circuit the noise canceller consists of five latch circuits connected in series, and a match detection circuit. when the noise canceller function is disabled (ncs = 0), the system clock is selected as the sampling clock. when the noise canceller is enabled (ncs = 1), the internal clock selected by bits cks1 and cks0 in tmg becomes the sampling clock. the input signal is sampled at the rising edge of this clock pulse. data is considered correct when the outputs of all five latch circuits match. if they do not match, the previous value is retained. upon reset, the noise canceller output is initialized after the falling edge of the input capture signal has been sampled five times. accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times greater than the sampling clock will be recognized as input capture signals. if the noise canceller circuit is not used, the input capture signal pulse width must be at least 2 f or 2 f sub in order to ensure proper input capture operation. note: * rewriting the ncs bit may cause an internal input capture signal to be generated. figure 9.10 shows a typical timing diagram for the noise canceller circuit. in this example, a high- level input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock f cycles. 217 input capture input signal sampling clock noise canceller output rejected as noise figure 9.10 noise canceller circuit timing (example) 9.6.4 timer operation timer g is an 8-bit timer with input capture and interval timer functions. timer g functions: timer g is an 8-bit timer/counter that functions as an input capture timer or an interval timer. these two functions are described below. input capture timer operation timer g functions as an input capture timer when bit tmig of port mode register 1 (pmr1) is set to 1.* at reset, timer mode register g (tmg), timer counter g (tcg), input capture register gf (icrgf), and input capture register gr (icrgr) are all initialized to h'00. immediately after reset, tcg begins counting an internal clock with a frequency of f divided by 64 ( f /64). four other internal clocks can be selected using bits cks1 and cks0 of tmg. at the rising edge/falling edge of the input capture signal input to pin tmig, the value of tcg is copied into icrgr/icrgf. if the input edge is the same as the edge selected by the iiegs bit of tmg, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, a cpu interrupt is requested. for details on interrupts, see section 3.3, interrupts. tcg can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal as determined with bits cclr1 and cclr0 of tmg. if tcg overflows while the input capture signal is high, bit ovfh of tmg is set. if tcg overflows while the input capture signal is low, bit ovfl of tmg is set. when either of these bits is set, if bit ovie of tmg is currently set to 1, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, then timer g requests a cpu interrupt. for further details see 3.3, interrupts. timer g has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin tmig. see 9.6.3, noise canceller circuit, for details. 218 note: * rewriting the tmig bit may cause an internal input capture signal to be generated. interval timer operation timer g functions as an interval timer when bit tmig is cleared to 0 in pmr1. following a reset, tcg starts counting cycles of the f /64 internal clock. this is one of four internal clock sources that can be selected by bits cks1 and cks0 of tmg. tcg counts up according to the selected clock source. when it overflows from h'ff to h'00, bit ovfl of tmg is set to 1. if bit ovie of tmg is currently set to 1, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, then timer g requests a cpu interrupt. for further details see 3.3, interrupts. count timing: tcg is incremented by input pulses from an internal clock. tmg bits cks1 and cks0 select one of four internal clocks ( f /64, f /32, f /2, f w /2) derived by dividing the system clock ( f ) or the watch clock ( f w ). timing of internal input capture signals: timing with noise canceller function disabled separate internal input capture signals are generated from the rising and falling edges of the external input signal. figure 9.11 shows the timing of these signals. external input capture signal internal input capture signal f internal input capture signal r figure 9.11 input capture signal timing (noise canceller function disabled) timing with noise canceller function enabled when input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. figure 9.12 shows the timing. 219 external input capture signal sampling clock noise canceller circuit output internal input capture signal r figure 9.12 input capture signal timing (noise canceller function enabled) timing of input capture: figure 9.13 shows the input capture timing in relation to the internal input capture signal. internal input capture signal tcg input capture register n ? n n +1 h'xx n figure 9.13 input capture timing 220 tcg clear timing: tcg can be cleared at the rising edge, falling edge, or both edges of the external input capture signal. figure 9.14 shows the timing for clearing at both edges. external input capture signal internal input capture signal f internal input capture signal r tcg n h'00 n h'00 figure 9.14 tcg clear timing timer g operation states: table 9.16 summarizes the timer g operation states. table 9.16 timer g operation states operation mode reset active sleep watch sub- active sub- sleep standby tcg input capture reset functions * functions * halted functions/ halted * functions/ halted * halted interval reset functions * functions * retained functions/ halted * functions/ halted * halted icrgf reset functions * functions * retained functions/ halted * functions/ halted * retained icrgr reset functions * functions * retained functions/ halted * functions/ halted * retained tmg reset functions retained retained functions retained retained note: * in active mode and sleep mode, if f w /2 is selected as the tcg internal clock, since the system clock and internal clock are not synchronized with each other, a synchronization circuit is used. this may result in a count cycle error of up to 1/ f (s). in subactive mode and subsleep mode, if f w /2 is selected as the tcg internal clock, regardless of the subclock f / sub ( f w /2, f w /4, f w /8) tcg and the noise canceller circuit run on an internal clock of f w /2. if any other internal clock is chosen, tcg and the noise canceller circuit will not run, and the input capture function will not operate. 221 9.6.5 application notes input clock switching and tcg operation: depending on when the input clock is switched, there will be cases in which tcg is incremented in the process. table 9.17 shows the relation between internal clock switchover timing (selected in bits cks1 and cks0) and tcg operation. if an internal clock (derived from the system clock f or subclock f sub ) is used, an increment pulse is generated when a falling edge of the internal clock is detected. for this reason, in a case like no. 3 in table 9.17, where the clock is switched at a time such that the clock signal goes from high level before switching to low level after switching, the switchover is seen as a falling edge, a count clock pulse is generated, and tcg is incremented. table 9.17 internal clock switching and tcg operation no. clock level before and after modifying bits cks1 and cks0 tcg operation 1 goes from low level to low level n +1 clock before switching clock after switching count clock tcg cks bits modified n 2 goes from low level to high level n +1 n +2 clock before switching clock after switching count clock tcg cks bits modified n 222 table 9.17 internal clock switching and tcg operation no. clock level before and after modifying bits cks1 and cks0 tcg operation 3 goes from high level to low level n +1 n n +2 * clock before switching clock after switching count clock tcg cks bits modified 4 goes from high level to high level n +1 n +2 n clock before switching clock after switching count clock cks bits modified tcg note: * the switchover is seen as a falling edge of the clock pulse, and tcg is incremented. note on rewriting port mode registers: when a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. switching the function of the input capture pin when the function of the input capture pin is switched by modifying the tmig bit in port mode register 1 (pmr1) an input capture edge may be recognized even though no valid signal edge has been input. this occurs under the conditions listed in table 9.18. 223 table 9.18 input capture input signal input edges and conditions by switching of input capture pin function input capture edge conditions rising edge recognized tmig pin level is high, and tmig bit is changed from 0 to 1 tmig pin level is high and ncs bit is changed from 0 to 1, then tmig bit is changed from 0 to 1 before noise canceller circuit completes five samples falling edge recognized tmig pin level is high, and tmig bit is changed from 1 to 0 tmig pin level is low and ncs bit is changed from 0 to 1, then tmig bit is changed from 0 to 1 before noise canceller circuit completes five samples tmig pin level is high and ncs bit is changed from 0 to 1, then tmig bit is changed from 1 to 0 before noise canceller circuit completes five samples note: when pin p1 3 is not used for input capture, the input capture signal input to timer g is low. switching the input capture noise canceling function when modifying the ncs bit in port mode register 2 (pmr2) to enable or disable the input capture noise canceling function, first clear the tmig bit to 0. otherwise an input capture edge may be recognized even though no valid signal edge has been input. this occurs under the conditions listed in table 9.19. table 9.19 input capture input signal input edges and conditions by switching of noise canceling function input capture edge conditions rising edge recognized tmig bit is set to 1 and tmig pin level changes from low to high, then ncs bit is changed from 1 to 0 before noise canceller circuit completes five samples falling edge recognized tmig bit is set to 1 and tmig pin level changes from high to low, then ncs bit is changed from 1 to 0 before noise canceller circuit completes five samples if switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (iiegs), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. figure 9.15 shows the procedure for modifying port mode register settings and clearing the interrupt request flag. the first step is to mask interrupts before modifying the port mode register. after modifying the port mode register setting, wait long enough for an input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear the interrupt request flag to 0 (assuming it has been set to 1). an alternative procedure is to avoid having the interrupt request flag set 224 when the pin function is switched, either by controlling the level of the input capture pin so that it does not satisfy the conditions in tables 9.18 and 9.19, or by setting the iiegs bit of tmg to select the edge opposite to the falsely generated edge. set i bit to 1 in ccr clear i bit to 0 in ccr modify port mode register wait for tmig to be recognized clear interrupt request flag to 0 disable interrupts (or disable by clearing interrupt enable bit in interrupt enable register 2) modify port mode register setting, wait for tmig to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear interrupt request flag to 0 enable interrupts figure 9.15 procedure for modifying port mode register and clearing interrupt request flag 9.6.6 sample timer g application the absolute values of the high and low widths of the input capture signal can be measured by using timer g. the cclr1 and cclr0 bits of tmg should be set to 1. figure 9.16 shows an example of this operation. input capture signal h'ff input capture register gf input capture register gr h'00 counter cleared tcg figure 9.16 sample timer g application 225 section 10 serial communication interface 10.1 overview the h8/3834 series is provided with a three-channel serial communication interface (sci). table 10.1 summarizes the functions and features of the three sci channels. table 10.1 serial communication interface functions channel functions features sci1 synchronous serial transfer choice of 8-bit or 16-bit data length continuous clock output choice of 8 internal clocks ( f /1024 to f /2) or external clock open drain output possible interrupt requested at completion of transfer sci2 synchronous serial transfer automatic transfer of up to 32 bytes of data (send, receive, or simultaneous send/receive) chip select input strobe pulse output choice of 7 internal clocks ( f /256 to f /2) or external clock open drain output possible interrupt requested at completion of transfer or error sci3 synchronous serial transfer 8-bit data transfer send, receive, or simultaneous send/receive asynchronous serial transfer multiprocessor communication function choice of 7-bit or 8-bit data length choice of 1-bit or 2-bit stop bit length parity addition built-in baud rate generator receive error detection break detection interrupt requested at completion of transfer or error 10.2 sci1 10.2.1 overview serial communication interface 1 (sci1) performs synchronous serial transfer of 8-bit or 16-bit data. 226 features choice of 8-bit or 16-bit data length choice of eight internal clock sources ( f /1024, f /256, f /64, f /32, f /16, f /8, f /4, f /2) or an external clock interrupt requested at completion of transfer block diagram figure 10.1 shows a block diagram of sci1. f sck 1 si 1 so 1 scr1 scsr1 sdru sdrl pss transfer bit counter transmit/receive control circuit internal data bus notation: scr1: scsr1: sdru: sdrl: irrs1: pss: serial control register 1 serial control/status register 1 serial data register u serial data register l sci1 interrupt request flag prescaler s irrs1 figure 10.1 sci1 block diagram 227 pin configuration table 10.2 shows the sci1 pin configuration. table 10.2 pin configuration name abbrev. i/o function sci1 clock pin sck 1 i/o sci1 clock input or output sci1 data input pin si 1 input sci1 receive data input sci1 data output pin so 1 output sci1 transmit data output register configuration table 10.3 shows the sci1 register configuration. table 10.3 sci1 registers name abbrev. r/w initial value address serial control register 1 scr1 r/w h'00 h'ffa0 serial control status register 1 scsr1 r/w h'80 h'ffa1 serial data register u sdru r/w not fixed h'ffa2 serial data register l sdrl r/w not fixed h'ffa3 10.2.2 register descriptions serial control register 1 (scr1) bit 76543210 snc1 snc0 cks3 cks2 cks1 cks0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w scr1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. upon reset, scr1 is initialized to h'00. writing to this register during a transfer stops the transfer. 228 bits 7 and 6operation mode select 1, 0 (snc1, snc0): bits 7 and 6 select the operation mode. bit 7: snc1 bit 6: snc0 description 0 0 8-bit synchronous transfer mode (initial value) 1 16-bit synchronous transfer mode 1 0 continuous clock output mode * 1 1 reserved * 2 notes: 1. pins si 1 and so 1 should be used as general input or output ports. 2. dont set bits snc1 and snc0 to 11. bits 5 and 4reserved bits: bits 5 and 4 are reserved, but they can be written and read. bit 3clock source select 3 (cks3): bit 3 selects the clock source and sets pin sck 1 as an input or output pin. bit 3: cks3 description 0 clock source is prescaler s, and pin sck 1 is output pin (initial value) 1 clock source is external clock, and pin sck 1 is input pin bits 2 to 0clock select 2 to 0 (cks2 to cks 0): when cks3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. serial clock cycle bit 2: cks2 bit 1: cks1 bit 0: cks0 prescaler division f = 5 mhz f = 2.5 mhz 000 f /1024 (initial value) 204.8 s 409.6 s 1 f /256 51.2 s 102.4 s 10 f /64 12.8 s 25.6 s 1 f /32 6.4 s 12.8 s 100 f /16 3.2 s 6.4 s 1 f /8 1.6 s 3.2 s 10 f /4 0.8 s 1.6 s 1 f /2 0.8 s 229 serial control/status register 1 (scsr1) bit 76543210 sol orer stf initial value 10000000 read/write r/w r/(w) * r/w r/w note: * only a write of 0 for flag clearing is possible. scsr1 is an 8-bit read/write register indicating operation status and error status. upon reset, scsr1 is initialized to h'80. bit 7reserved bit: bit 7 is reserved; it is always read as 1, and cannot be modified. bit 6extended data bit (sol): bit 6 sets the so 1 output level. when read, sol returns the output level at the so 1 pin. after completion of a transmission, so 1 continues to output the value of the last bit of transmitted data. the so 1 output can be changed by writing to sol before or after a transmission. the sol bit setting remains valid only until the start of the next transmission. to control the level of the so 1 pin after transmission ends, it is necessary to write to the sol bit at the end of each transmission. do not write to this register while transmission is in progress, because that may cause a malfunction. bit 6: sol description 0 read: so 1 pin output level is low (initial value) write: so 1 pin output level changes to low 1 read: so 1 pin output level is high write: so 1 pin output level changes to high bit 5overrun error flag (orer): when an external clock is used, bit 5 indicates the occurrence of an overrun error. if a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. if noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. bit 5: orer description 0 clearing conditions: after reading orer = 1, cleared by writing 0 to orer (initial value) 1 setting conditions: set if a clock pulse is input after transfer is complete, when an external clock is used 230 bits 4 to 2reserved bits: bits 4 to 2 are reserved; they are always read as 0, and cannot be modified. bit 1reserved bit: bit 1 is reserved; it should always be cleared to 0. bit 0start flag (stf): bit 0 controls the start of a transfer. setting this bit to 1 causes sci1 to start transferring data. during the transfer or while waiting for the first clock pulse, this bit remains set to 1. it is cleared to 0 upon completion of the transfer. it can therefore be used as a busy flag. bit 0: stf description 0 read: indicates that transfer is stopped (initial value) write: invalid 1 read: indicates transfer in progress write: starts a transfer operation serial data register u (sdru) bit 76543210 sdru7 sdru6 sdru5 sdru4 sdru3 sdru2 sdru1 sdru0 initial value not fixed not fixed not fixed not fixed not fixed not fixed not fixed not fixed read/write r/w r/w r/w r/w r/w r/w r/w r/w sdru is an 8-bit read/write register. it is used as the data register for the upper 8 bits in 16-bit transfer (sdrl is used for the lower 8 bits). data written to sdru is output to sdrl starting from the least significant bit (lsb). this data is then replaced by lsb-first data input at pin si 1 , which is shifted in the direction from the most significant bit (msb) toward the lsb. sdru must be written or read only after data transmission or reception is complete. if this register is written or read while a data transfer is in progress, the data contents are not guaranteed. the sdru value upon reset is not fixed. 231 serial data register l (sdrl) bit 76543210 sdrl7 sdrl6 sdrl5 sdrl4 sdrl3 sdrl2 sdrl1 sdrl0 initial value not fixed not fixed not fixed not fixed not fixed not fixed not fixed not fixed read/write r/w r/w r/w r/w r/w r/w r/w r/w sdrl is an 8-bit read/write register. it is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (sdru is used for the upper 8 bits). in 8-bit transfer, data written to sdrl is output from pin so 1 starting from the least significant bit (lsb). this data is than replaced by lsb-first data input at pin si 1 , which is shifted in the direction from the most significant bit (msb) toward the lsb. in 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via sdru. sdrl must be written or read only after data transmission or reception is complete. if this register is read or written while a data transfer is in progress, the data contents are not guaranteed. the sdrl value upon reset is not fixed. 10.2.3 operation data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external serial clock. overrun errors can be detected when an external clock is used. clock the serial clock can be selected from a choice of eight internal clocks and an external clock. when an internal clock source is selected, pin sck 1 becomes the clock output pin. when continuous clock output mode is selected (scr1 bits snc1 and snc0 are set to 10), the clock signal ( f /1024 to f /2) selected in bits cks2 to cks0 is output continuously from pin sck 1 . when an external clock is used, pin sck 1 is the clock input pin. data transfer format figure 10.2 shows the data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. 232 sck so /si 1 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 10.2 transfer format data transfer operations transmitting: a transmit operation is carried out as follows. set bits so1 and sck1 in pmr3 to 1 so that the respective pins function as so 1 and sck 1 . if necessary, set bit pof1 in port mode register 2 (pmr2) for nmos open drain output at pin so 1 . clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. write transmit data in sdrl and sdru, as follows. ? 8-bit transfer mode: sdrl ? 16-bit transfer mode: upper byte in sdru, lower byte in sdrl set the scsr1 start flag (stf) to 1. sci1 starts operating and outputs transmit data at pin so 1 . after data transmission is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted in synchronization with the serial clock input at pin sck 1 . after data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. receiving: a receive operation is carried out as follows. set bits si1 and sck1 in pmr3 to 1 so that the respective pins function as si 1 and sck 1 . clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. set the scsr1 start flag (stf) to 1. sci1 starts operating and receives data at pin si 1 . after data reception is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. 233 read the received data from sdrl and sdru, as follows. ? 8-bit transfer mode: sdrl ? 16-bit transfer mode: upper byte in sdru, lower byte in sdrl after data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the scsr1 overrun error flag (bit orer) is set to 1. simultaneous transmit/receive: a simultaneous transmit/receive operation is carried out as follows. set bits so1, si1, and sck1 in pmr3 to 1 so that the respective pins function as so 1 , si 1 , and sck 1 . if necessary, set bit pof1 in port mode register 2 (pmr2) for nmos open drain output at pin so 1 . clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. write transmit data in sdrl and sdru, as follows. ? 8-bit transfer mode: sdrl ? 16-bit transfer mode: upper byte in sdru, lower byte in sdrl set the scsr1 start flag (stf) to 1. sci1 starts operating. transmit data is output at pin so 1 . receive data is input at pin si 1 . after data transmission and reception are complete, bit irrs1 in irr1 is set to 1. read the received data from sdrl and sdru, as follows. ? 8-bit transfer mode: sdrl ? 16-bit transfer mode: upper byte in sdru, lower byte in sdrl when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin sck 1 . after data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. 234 10.2.4 interrupts sci1 can generate an interrupt at the end of a data transfer. when an sci1 transfer is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. sci1 interrupt requests can be enabled or disabled by bit iens1 of interrupt enable register 1 (ienr1). for further details, see 3.3, interrupts. 10.2.5 application notes when an external clock is input at pin sck 1 , and an external clock is selected for use as the clock source bit stf in scsr1 must first be set to 1 to start data transfer before inputting the external clock. 10.3 sci2 10.3.1 overview serial communication interface 2 (sci2) has a 32-bit data buffer for synchronous serial transfer of up to 32 bytes of data in one operation. features features of sci are listed below. automatic transfer of up to 32 bytes of data choice of seven internal clock sources ( f /256, f /64, f /32, f /16, f /8, f /4, f /2) or an external clock interrupts requested at completion of transfer or when an error occurs gaps of 56, 24, or 8 internal clock cycles can be inserted between successive bytes of transferred data. transfer can be started by chip select input. a strobe pulse can be output for each byte transferred. 235 block diagram figure 10.3 shows a block diagram of sci2. sck strb cs so si pss star edar scr2 scsr2 transmit/receive control circuit shift register serial data buffer internal data bus notation: star: edar: irrs2: pss: start address register end address register sci2 interrupt request flag (irr2) prescaler s irrs2 2 2 2 figure 10.3 sci2 block diagram pin configuration table 10.4 shows the sci2 pin configuration. 236 table 10.4 pin configuration name abbrev. i/o function sci2 clock pin sck 2 i/o sci2 clock input/output sci2 data input pin si 2 input sci2 receive data input sci2 data output pin so 2 output sci2 transmit data output sci2 strobe pin strb output sci2 strobe signal output sci2 chip select pin cs input sci2 chip select signal input register configuration table 10.5 shows the sci2 register configuration. table 10.5 sci2 registers name abbrev. r/w initial value address start address register star r/w h'e0 h'ffa4 end address register edar r/w h'e0 h'ffa5 serial control register 2 scr2 r/w h'e0 h'ffa6 serial control/status register 2 scsr2 r/w h'e0 h'ffa7 serial data buffer (32 bytes) r/w not fixed h'ff80 to h'ff9f 10.3.2 register descriptions start address register (star) bit 76543210 sta4 sta3 sta2 sta1 sta0 initial value 11100000 read/write r/w r/w r/w r/w r/w star is an 8-bit read/write register, for designating a transfer start address in the address space (h'ff80 to h'ff9f) allocated to the 32-byte data buffer. the lower 5 bits of star correspond to the lower 5 bits of the address. the extent of continuous data transfer is defined in star and in the end address register (edar). if the same value is designated by star and edar, only 1 byte of data is transferred. bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. upon reset, star is initialized to h'e0. 237 end address register (edar) bit 76543210 eda4 eda3 eda2 eda1 eda0 initial value 11100000 read/write r/w r/w r/w r/w r/w edar is an 8-bit read/write register, for designating a transfer end address in the address space (h'ff80 to h'ff9f) allocated to the 32-byte data buffer. the lower 5 bits of edar correspond to the lower 5 bits of the address. the extent of continuous data transfer is defined in star and in edar. if the same value is designated by star and edar, only 1 byte of data is transferred. bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. upon reset, edar is initialized to h'e0. serial control register 2 (scr2) bit 76543210 gap1 gap0 cks2 cks1 cks0 initial value 11100000 read/write r/w r/w r/w r/w r/w scr2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted between data during continuous transfer when sci2 uses an internal clock. upon reset, scr2 is initialized to h'e0. bits 7 to 5reserved bits: bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. bits 4 and 3gap select 1, 0 (gap1 to gap0): when sci2 uses an internal clock, gaps can be inserted between successive data bytes. bits 4 and 3 designate the length of these gaps. during a gap, pin sck 2 remains at the high level. when no gap is inserted, the strb signal stays at the low level. bit 4: gap1 bit 3: gap0 description 0 0 no gaps between bytes (initial value) 1 a gap of 8 clock cycles is inserted between bytes 1 0 a gap of 24 clock cycles is inserted between bytes 1 a gap of 56 clock cycles is inserted between bytes 238 bits 2 to 0clock select 2 to 0 (cks2 to cks0): bits 2 to 0 select one of seven internal clock sources or an external clock as the transfer clock. bit 2: bit 1: bit 0: clock prescaler serial clock cycle cks2 cks1 cks0 pin sck 2 source division f = 5 mhz f = 2.5 mhz 000sck 2 output prescaler s f /256 (initial value) 51.2 s 102.4 s 1 f /64 12.8 s 25.6 s 10 f /32 6.4 s 12.8 s 1 f /16 3.2 s 6.4 s 100 f /8 1.6 s 3.2 s 1 f /4 0.8 s 1.6 s 10 f /2 0.8 s 1 sck 2 input external clock serial control/status register 2 (scsr2) bit 76543210 sol orer wt abt stf initial value 11100000 read/write r/w r/(w) * r/(w) * r/(w) * r/w note: * only a write of 0 for flag clearing is possible. scsr2 is an 8-bit register indicating sci2 operation status and error status. upon reset, scsr2 is initialized to h'e0. bits 7 to 5reserved bits: bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. bit 4extended data bit (sol): bit 4 sets the so 2 output level. when read, sol returns the transmitted data output at the so 2 pin. after completion of a transmission, so 2 continues to output the value of the last bit of transmitted data. the so 2 output can be changed by writing to sol before or after a transmission. the sol bit setting remains valid only until the start of the next transmission. to control the level of the so 2 pin after transmission ends, it is necessary to write to the sol bit at the end of each transmission. note that if the stf bit is cleared to 0 to terminate a transmission in progress, the transmitted data will be modified when the bit is cleared. 239 bit 4: sol description 0 read: so 2 pin output level is low (initial value) write: so 2 pin output level changes to low 1 read: so 2 pin output level is high write: so 2 pin output level changes to high bit 3overrun error flag (orer): when an external clock is used, bit 3 indicates the occurrence of an overrun error. if a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. if noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. overrun errors are not detected while pin cs is at the high level. bit 3: orer description 0 clearing conditions: after reading orer = 1, cleared by writing 0 to orer (initial value) 1 setting conditions: set if a clock pulse is input after transfer is complete, when an external clock is used bit 2wait flag (wt): bit 2 indicates that an attempt was made to read or write the 32-byte serial data buffer while a transfer was in progress, or while waiting for cs input. the read or write access is not carried out, and this bit is set to 1. bit 2: wt description 0 clearing conditions: after reading wt = 1, cleared by writing 0 to wt (initial value) 1 setting conditions: an attempt was made to read or write the (32-byte) serial data buffer during a transfer operation or while waiting for cs input bit 1abort flag (abt): bit 1 indicates that cs went to high during data transfer. when the cs input function is selected, if a high-level signal is detected at pin cs during a transfer, the transfer is immediately aborted and this bit is set to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) is set to 1, and pins sck 2 and so 2 go to the high-impedance state. data in the (32-byte) serial data buffer and values in the internal registers other than scsr2 remain unchanged. transfer cannot take place while this bit is set to 1. it must be cleared to 0 before resuming the transfer. 240 bit 1: abt description 0 clearing conditions: after reading abt = 1, cleared by writing 0 to abt (initial value) 1 setting conditions: when pin cs goes high during a transfer bit 0start flag (stf): bit 0 controls the start of a transfer. if bit cs = 0 in pmr2, setting bit stf to 1 causes sci2 to start transferring data. if bit cs = 1 in pmr2, sci2 starts transferring data when cs goes low. this bit stays at 1 during the transfer or while waiting for cs input; it is cleared to 0 after the transfer is completed or when the transfer is aborted by cs . it can therefore be used as a busy flag. clearing this bit to 0 during a transfer aborts the transfer. the contents of the (32-byte) serial data buffer and of internal registers other than scsr2 remain unchanged. bit 0: stf description 0 read: indicates that transfer is stopped (initial value) write: stops a transfer operation 1 read: indicates transfer in progress or waiting for cs input write: starts a transfer operation 10.3.3 operation sci2 has a 32-byte serial data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. sci2 transmits and receives data in synchronization with clock pulses. depending on register settings, it can transmit, receive, or transmit and receive simultaneously. when transmission is set, the serial data buffer values are retained after the transmission is completed. either an internal clock or external clock may be selected as the serial clock. when an internal clock is selected, gaps may be inserted between the data bytes. it is also possible to output a strobe signal at pin strb. when an external clock is selected, the overrun flag allows detection of erroneous operation due to unwanted clock input. transfers can be started or aborted by input at pin cs . abort is indicated by means of an abort flag. clock the serial clock can be selected from a choice of six internal clock sources or an external clock. when an internal clock source is selected, pin sck 2 becomes the clock output pin. 241 data transfer format figure 10.4 and figure 10.5 show the sci2 data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. when sci2 operates on an internal clock, a gap can be inserted between each byte of transferred data and the next, as shown in figure 10.5. during this gap, pin sck 2 output remains high. also, a strobe pulse can be output at pin strb. the length of the gap is designated in bits gap1 and gap0 in serial control register 2 (scr2). 242 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 transfer started transfer completed sck so /si cs strb 2 22 figure 10.4 data transfer format (no gaps between data) 243 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 sck so /si cs strb 2 22 transfer started transfer completed 8, 24, or 56 clock cycles figure 10.5 data transfer format (gap inserted between data) 244 data transfer operations sci2 initialization: data transfer on sci2 first of all requires that sci2 be initialized by software as follows. with bit stf cleared to 0 in scsr2, select pin functions and the transfer mode in registers pmr2, pmr3, star, edar, and scr2. the sci2 pins double as general input/output ports. switching between port and sci2 functions is controlled in pmr3. cmos output or nmos open drain output can be selected in pmr2. the serial clock and gaps between transferred bytes are set in scr2. the start and end addresses of the transfer data area are set in star and edar. if the end address is set smaller than the start address, as shown in figure 10.6, the transfer wraps around from h'ff9f to h'ff80 and continues to the end address. if the start address and end address are the same, only one byte of data will be transferred. h'ff80 h'ff9f end address start address end start figure 10.6 operation when end address is smaller than start address transmitting: a transmit operation is carried out as follows. set bits so2 and sck2 in pmr3 to 1 so that the respective pins function as so 2 and sck 2 . if necessary, set bit pof2 in port mode register 2 (pmr2) for nmos open-drain output at pin so 2 , and set bits cs and strb in pmr3 to designate use of the cs and strb pin functions. select the serial clock and, in the case of internal clock operation, the data gap in scr2. write transmit data in the serial data buffer. this data will remain in the data buffer after completion of the transfer. it is not necessary to rewrite the buffer when the same data is retransmitted. set the start address in the lower 5 bits of star, and the end address in the lower 5 bits of edar. set the start/busy flag (stf) to 1. if bit cs = 0 in pmr3, transmission starts as soon as stf is set to 1. if cs = 1 in pmr3, transmission starts when cs goes low. after data transmission is complete, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. 245 when an internal clock is used, a serial clock is output from pin sck 2 in synchronization with the transmit data. after data transmission is completed, the serial clock is not output until bit stf is set again. during this time, pin so 2 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted in synchronization with the serial clock input at pin sck 2 . after data transmission is completed, an overrun occurs if the serial clock continues to be input; no data is transmitted and the scsr2 overrun error flag (bit orer) is set to 1. pin so 2 continues to output the value of the last preceding bit. overrun errors are not detected when both pin cs is at the high level and pmr3 bit cs = 1. while transmission is stopped, the output value of pin so 2 can be changed by rewriting bit sol in scsr2. during a transmission or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed, the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set to 1. if bit cs = 1 in pmr3 and during transmission a high-level signal is detected at pin cs , the transmit operation will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. receiving: a receive operation is carried out as follows. set bits si2 and sck2 in port mode register 3 (pmr3) to 1, designating use of the si 2 and sck 2 pin functions. if necessary, set bit cs in pmr3 to select the cs pin function. select the serial clock and, in the case of internal clock operation, the data gap in scr2. allocate an area to hold the received data in the serial data buffer by designating the receive start address in the lower 5 bits of the start address register (star) and the receive end address in the lower 5 bits of the end address register (edar). set the start/busy flag (bit stf) to 1. if bit cs = 0 in pmr3, receiving starts as soon as stf is set. if cs = 1 in pmr3, receiving starts when cs goes low. after receiving is completed, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. read the received data from the serial data buffer. if an internal clock is used, a serial clock is output from pin sck 2 when the receive operation starts. after receiving is completed, the serial clock is not output until bit stf is set again. when an external clock source is used, data is received in synchronization with the clock input at pin sck 2 . after receiving is completed, an overrun occurs if the serial clock continues to be input; no further data is received and the scsr2 overrun error flag (bit orer) is set to 1. overrun errors are not detected when both pin cs is high and bit cs = 1 in pmr3. 246 while receiving or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set. if bit cs = 1 in pmr3 and a high-level signal is detected at pin cs during receiving, the receive operation will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. simultaneous transmit/receive: a simultaneous transmit/receive operation is carried out as follows. set bits so2, si2, and sck2 in pmr3 to 1, designating use of the so 2 , si 2 , and sck 2 pin functions. if necessary, set bit pof2 in port mode register 2 (pmr2) for nmos open-drain output at pin so 2 , and set bits cs and strb to designate use of the cs and strb pin functions. select the transfer clock and, in the case of internal clock operation, the data gap in scr2. write transmit data in the serial data buffer. in simultaneous transmit/receive, received data replaces transmitted data at the same buffer addresses. set the transfer start address in the lower 5 bits of star, and the transfer end address in the lower 5 bits of edar. set the start/busy flag (bit stf) to 1. if bit cs = 0 in pmr3, the transfer starts as soon as stf is set. if cs = 1 in pmr3, transfer operations start when cs goes low. after data transfer is completed, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. read the received data from the serial data buffer. if an internal clock is used, a serial clock is output from pin sck 2 when the transfer begins. after the transfer is completed, the serial clock is not output until bit stf is set again. during this time, pin so 2 continues to output the value of the last bit transmitted. when an external clock is used, data is transferred in synchronization with the serial clock input at pin sck 2 . after the transfer is completed, an overrun occurs if the serial clock continues to be input; no transfer operation takes place and the scsr2 overrun error flag (bit orer) is set to 1. pin so 2 continues to output the value of the last transmitted bit. overrun errors are not detected when both pin cs is high and bit cs = 1 in pmr3. while data transfer is stopped, the output value of pin so 2 can be changed by rewriting bit sol in scsr2. 247 during a transfer or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set. if bit cs = 1 in pmr3 and during the transfer a high-level signal is detected at pin cs, the transfer will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. 10.3.4 interrupts sci2 can generate interrupts when a transfer is completed or when a transfer is aborted by cs. these interrupts have the same vector address. when the above conditions occur, bit irrs2 in interrupt request register 2 (irr2) is set to 1. sci2 interrupt requests can be enabled or disabled in bit iens2 of interrupt enable register 2 (ienr2). for further details, see 3.3, interrupts. when a transfer is aborted by cs , an overrun error occurs, or a read or write of the serial data buffer is attempted during a transfer or while waiting for cs input, the abt, orer, or wt bit in scsr2 is set to 1. these bits can be used to determine the cause of the error. 10.3.5 application notes when an external clock is input at pin sck 2 , and an external clock is selected for use as the clock source bit stf in scsr2 must first be set to 1 to start data transfer before inputting the external clock. 248 10.4 sci3 10.4.1 overview serial communication interface 3 (sci3) has both synchronous and asynchronous serial data communication capabilities. it also has a multiprocessor communication function for serial data communication among two or more processors. features sci3 features are listed below. selection of asynchronous or synchronous mode ? asynchronous mode serial data communication is performed using an asynchronous method in which synchronization is established character by character. sci3 can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. data length: seven or eight bits stop bit length: one or two bits parity: even, odd, or none multiprocessor bit: one or none receive error detection: parity, overrun, and framing errors break detection: by reading the rxd level directly when a framing error occurs ? synchronous mode serial data communication is synchronized with a clock signal. sci3 can communicate with other chips having a clocked synchronous communication function. data length: eight bits receive error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so sci3 can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. built-in baud rate generator with selectable bit rates. internal or external clock may be selected as the transfer clock source. there are six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error. 249 block diagram figure 10.7 shows a block diagram of sci3. sck txd rxd 3 tsr rsr rdr tdr ssr scr3 smr brr brc external clock baud rate generator internal clock ( /64, /16, /4, ) clock transmit/receive control internal data bus interrupt requests (tei, txi, rxi, eri) notation: rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter ffff figure 10.7 sci3 block diagram 250 pin configuration table 10.6 shows the sci3 pin configuration. table 10.6 pin configuration name abbrev. i/o function sci3 clock sck 3 i/o sci3 clock input/output sci3 receive data input rxd input sci3 receive data input sci3 transmit data output txd output sci3 transmit data output register configuration table 10.7 shows the sci3 internal register configuration. table 10.7 sci3 registers name abbrev. r/w initial value address serial mode register smr r/w h'00 h'ffa8 bit rate register brr r/w h'ff h'ffa9 serial control register 3 scr3 r/w h'00 h'ffaa transmit data register tdr r/w h'ff h'ffab serial status register ssr r/w h'84 h'ffac receive data register rdr r h'00 h'ffad transmit shift register tsr * receive shift register rsr * bit rate counter brc * note: : cannot be read or written. 10.4.2 register descriptions receive shift register (rsr) bit 76543210 read/write the receive shift register (rsr) is for receiving serial data. 251 serial data is input in lsb (bit 0) order into rsr from pin rxd, converting it to parallel data. after each byte of data has been received, the byte is automatically transferred to the receive data register (rdr). rsr cannot be read or written directly by the cpu. receive data register (rdr) bit 76543210 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 initial value 00000000 read/write rrrrrrrr the receive data register (rdr) is an 8-bit register for storing received serial data. each time a byte of data is received, the received data is transferred from the receive shift register (rsr) to rdr, completing a receive operation. thereafter rsr again becomes ready to receive new data. rsr and rdr form a double buffer mechanism that allows data to be received continuously. rdr is exclusively for receiving data and cannot be written by the cpu. rdr is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. transmit shift register (tsr) bit 76543210 read/write the transmit shift register (tsr) is for transmitting serial data. transmit data is first transferred from the transmit data register (tdr) to tsr, then is transmitted from pin txd, starting from the lsb (bit 0). after one byte of data has been sent, the next byte is automatically transferred from tdr to tsr, and the next transmission begins. if no data has been written to tdr (1 is set in tdre), there is no data transfer from tdr to tsr. tsr cannot be read or written directly by the cpu. 252 transmit data register (tdr) bit 76543210 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w the transmit data register (tdr) is an 8-bit register for holding transmit data. when sci3 detects that the transmit shift register (tsr) is empty, it shifts transmit data written in tdr to tsr and starts serial data transmission. while tsr is transmitting serial data, the next byte to be transmitted can be written to tdr, realizing continuous transmission. tdr can be read or written by the cpu at all times. tdr is initialized to h'ff upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. serial mode register (smr) bit 76543210 com chr pe pm stop mp cks1 cks0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w the serial mode register (smr) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. smr can be read and written by the cpu at any time. smr is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7communication mode (com): bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode. bit 7: com description 0 asynchronous mode (initial value) 1 synchronous mode 253 bit 6character length (chr): bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. in synchronous mode the data length is always 8 bits regardless of the setting here. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected as the character length in asynchronous mode, the msb (bit 7) in the transmit data register is not transmitted. bit 5parity enable (pe): in asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. in synchronous mode there is no adding or checking of parity regardless of the setting here. bit 5: pe description 0 parity bit adding and checking disabled (initial value) 1 parity bit adding and checking enabled * note: * when pe is set to 1, then either odd or even parity is added to transmit data, depending on the setting of the parity mode bit (pm). when data is received, it is checked for odd or even parity as designated in bit pm. bit 4parity mode (pm): in asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data. the pm setting is valid only if bit pe is set to 1, enabling parity adding/checking. in synchronous mode, or if parity adding/checking is disabled in asynchronous mode, the pm setting is invalid. bit 4: pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an even number. when data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an even number. 2. when odd parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an odd number. when data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an odd number. 254 bit 3stop bit length (stop): bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. this setting is valid only in asynchronous mode. in synchronous mode a stop bit is not added, so this bit is ignored. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. when data is transmitted, one 1 bit is added at the end of each transmitted character as the stop bit. 2. when data is transmitted, two 1 bits are added at the end of each transmitted character as the stop bits. when data is received, only the first stop bit is checked regardless of the stop bit length. if the second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next character. bit 2multiprocessor mode (mp): bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is enabled, the parity enable (pe) and parity mode (pm) settings are ignored. the mp bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous mode. see 10.4.6, for details on the multiprocessor communication function. bit 2: mp description 0 multiprocessor communication function disabled (initial value) 1 multiprocessor communication function enabled bits 1 and 0clock select 1, 0 (cks1, cks0): bits 1 and 0 select the clock source for the built- in baud rate generator. a choice of f /64, f /16, f /4, or f is made in these bits. see 8, bit rate register (brr), below for information on the clock source and bit rate register settings, and their relation to the baud rate. bit 1: cks1 bit 0: cks0 description 00 f clock (initial value) 1 f /4 clock 10 f /16 clock 1 f /64 clock 255 serial control register 3 (scr3) bit 76543210 tie rie te re mpie teie cke1 cke0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w serial control register 3 (scr3) is an 8-bit register that controls sci3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. scr3 can be read and written by the cpu at any time. scr3 is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7transmit interrupt enable (tie): bit 7 enables or disables the transmit data empty interrupt (txi) request when data is transferred from tdr to tsr and the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1. the txi interrupt can be cleared by clearing bit tdre to 0, or by clearing bit tie to 0. bit 7: tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6receive interrupt enable (rie): bit 6 enables or disables the receive error interrupt (eri), and the receive data full interrupt (rxi) requested when data is transferred from rsr to rdr and the receive data register full bit (rdrf) in the serial status register (ssr) is set to 1. there are three kinds of receive error: overrun, framing, and parity. rxi and eri interrupts can be cleared by clearing ssr flag rdrf, or flags fer, per, and oer to 0, or by clearing bit rie to 0. bit 6: rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled 256 bit 5transmit enable (te): bit 5 enables or disables the start of a transmit operation. bit 5: te description 0 transmit operation disabled * 1 (txd is a general i/o port) (initial value) 1 transmit operation enabled * 2 (txd is the transmit data pin) notes: 1. the transmit data register empty bit (tdre) in the serial status register (ssr) is fixed at 1. 2. in this state, writing transmit data in tdr clears bit tdre in ssr to 0 and starts serial data transmission. before setting te to 1 it is necessary to set the transmit format in smr. bit 4receive enable (re): bit 4 enables or disables the start of a receive operation. bit 4: re description 0 receive operation disabled * 1 (rxd is a general i/o port) (initial value) 1 receive operation enabled * 2 (rxd is the receive data pin) notes: 1. when re is cleared to 0, this has no effect on the ssr flags rdrf, fer, per, and oer, which retain their states. 2. serial data receiving begins when, in this state, a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. before setting re to 1 it is necessary to set the receive format in smr. bit 3multiprocessor interrupt enable (mpie): bit 3 enables or disables multiprocessor interrupt requests. this setting is valid only in asynchronous mode, and only when the multiprocessor mode bit (mp) in the serial mode register (smr) is set to 1. this bit is ignored when com is set to 1 or when bit mp is cleared to 0. bit 3: mpie description 0 multiprocessor interrupt request disabled (ordinary receive operation) (initial value) clearing condition: multiprocessor bit receives a data value of 1 1 multiprocessor interrupt request enabled * note: * sci3 does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set status flags rdrf, fer, and oer in ssr. until a multiprocessor bit value of 1 is received, the receive data full interrupt (rxi) and receive error interrupt (eri) are disabled and serial status register (ssr) flags rdrf, fer, and oer are not set. when the multiprocessor bit receives a 1, the mpbr bit of ssr is set to 1, mpie is automatically cleared to 0, rxi and eri interrupts are enabled (provided bits tie and rie in scr3 are set to 1), and setting of the rdrf, fer, and oer flags is enabled. 257 bit 2transmit end interrupt enable (teie): bit 2 enables or disables the transmit end interrupt (tei) requested if there is no valid transmit data in tdr when the msb is transmitted. bit 2: teie description 0 transmit end interrupt (tei) disabled (initial value) 1 transmit end interrupt (tei) enabled * note: * a tei interrupt can be cleared by clearing the ssr bit tdre to 0 and clearing the transmit end bit (tend) to 0, or by clearing bit teie to 0. bits 1 and 0clock enable 1, 0 (cke1, cke0): bits 1 and 0 select the clock source and enable or disable clock output at pin sck 3 . the combination of bits cke1 and cke0 determines whether pin sck 3 is a general i/o port, a clock output pin, or a clock input pin. note that the cke0 setting is valid only when operation is in asynchronous mode using an internal clock (cke1 = 0). this bit is invalid in synchronous mode or when using an external clock (cke1 = 1). in synchronous mode and in external clock mode, clear cke0 to 0. after setting bits cke1 and cke0, the operation mode must first be set in the serial mode register (smr). see table 10.9 in 10.4.3, operation, for details on clock source selection. bit 1: cke1 bit 0: cke0 communication mode clock source sck 3 pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 0 1 asynchronous internal clock clock output * 2 synchronous reserved reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 1 asynchronous reserved reserved synchronous reserved reserved notes: 1. initial value 2. a clock is output with the same frequency as the bit rate. 3. input a clock with a frequency 16 times the bit rate. serial status register (ssr) bit 76543210 tdre rdrf oer fer per tend mpbr mpbt initial value 10000100 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written for flag clearing. 258 the serial status register (ssr) is an 8-bit register containing status flags for indicating sci3 states, and containing the multiprocessor bits. ssr can be read and written by the cpu at any time, but the cpu cannot write a 1 to the status flags tdre, rdrf, oer, per, and fer. to clear these flags to 0 it is first necessary to read a 1. bit 2 (tend) and bit 1 (mpbr) are read-only bits and cannot be modified. ssr is initialized to h'84 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7transmit data register empty (tdre): bit 7 is a status flag indicating that data has been transferred from tdr to tsr. bit 7: tdre description 0 indicates that transmit data written to tdr has not been transferred to tsr clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre. when data is written to tdr by an instruction. 1 indicates that no transmit data has been written to tdr, or the transmit data written to tdr has been transferred to tsr (initial value) setting conditions: when bit te in scr3 is cleared to 0. when data is transferred from tdr to tsr. bit 6receive data register full (rdrf): bit 6 is a status flag indicating whether there is receive data in rdr. bit 6: rdrf description 0 indicates there is no receive data in rdr (initial value) clearing conditions: after reading rdrf = 1, cleared by writing 0 to rdrf. when data is read from rdr by an instruction. 1 indicates that there is receive data in rdr setting condition: when receiving ends normally, with receive data transferred from rsr to rdr note: if a receive error is detected at the end of receiving, or if bit re in serial control register 3 (scr3) is cleared to 0, rdr and rdrf are unaffected and keep their previous states. an overrun error (oer) occurs if receiving of data is completed while bit rdrf remains set to 1. if this happens, receive data will be lost. 259 bit 5overrun error (oer): bit 5 is a status flag indicating that an overrun error has occurred during data receiving. bit 5: oer description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) clearing condition: after reading oer = 1, cleared by writing 0 to oer 1 indicates that an overrun error occurred in data receiving * 2 setting condition: when data receiving is completed while rdrf is set to 1 notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, oer is unaffected and keeps its previous state. 2. rdr keeps the data received prior to the overrun; data received after that is lost. while oer is set to 1, data receiving cannot be continued. in synchronous mode, data transmitting cannot be continued either. bit 4framing error (fer): bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. bit 4: fer description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) clearing condition: after reading fer = 1, cleared by writing 0 to fer 1 indicates that a framing error occurred in data receiving setting condition: the stop bit at the end of receive data is checked for a value of 1 and found to be 0 * 2 notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, fer is unaffected and keeps its previous state. 2. when two stop bits are used only the first stop bit is checked, not the second. when a framing error occurs, receive data is transferred to rdr but rdrf is not set. while fer is set to 1, data receiving cannot be continued. in synchronous mode, data transmitting cannot be continued either. 260 bit 3parity error (per): bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving. bit 3: per description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) clearing condition: after reading per = 1, cleared by writing 0 to per 1 indicates that a parity error occurred in data receiving * 2 setting condition: when the sum of 1s in received data plus the parity bit does not match the parity mode bit (pm) setting in the serial mode register (smr) notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, per is unaffected and keeps its previous state. 2. when a parity error occurs, receive data is transferred to rdr but rdrf is not set. while per is set to 1, data receiving cannot be continued. in synchronous mode, data transmitting cannot be continued either. bit 2transmit end (tend): bit 2 is a status flag indicating that tdre was set to 1 when the last bit of a transmitted character was sent. tend is a read-only bit and cannot be modified directly. bit 2: tend description 0 indicates that transmission is in progress clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre. when data is written to tdr by an instruction. 1 indicates that a transmission has ended (initial value) setting conditions: when bit te in scr3 is cleared to 0. if tdre is set to 1 when the last bit of a transmitted character is sent. bit 1multiprocessor bit receive (mpbr): bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format. mpbr is a read-only bit and cannot be modified. bit 1: mpbr description 0 indicates reception of data in which the multiprocessor bit is 0 * (initial value) 1 indicates reception of data in which the multiprocessor bit is 1 note: * if bit re is cleared to 0 while a multiprocessor format is in use, mpbr retains its previous state. 261 bit 0multiprocessor bit transmit (mpbt): bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. bit mpbt is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. bit 0: mpbt description 0 the multiprocessor bit in transmit data is 0 (initial value) 1 the multiprocessor bit in transmit data is 1 bit rate register (brr) bit 76543210 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w the bit rate register (brr) is an 8-bit register which, together with the baud rate generator clock selected by bits cks1 and cks0 in the serial mode register (smr), sets the transmit/receive bit rate. brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. table 10.8 gives examples of how brr is set in asynchronous mode. the values in table 10.8 are for active (high-speed) mode. 262 table 10.8 brr settings and bit rates in asynchronous mode osc (mhz) 2 2.4576 4 4.194304 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 C0.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 C0.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 C2.48 9600 0 3 0 0 6 C2.48 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0 table 10.8 brr settings and bit rates in asynchronous mode (cont) osc (mhz) 4.9152 6 7.3728 8 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 174 C0.26 1 212 +0.03 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 C2.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 C2.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 C2.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 263 table 10.8 brr settings and bit rates in asynchronous mode (cont) osc (mhz) 9.8304 10 bit rate (bits/s) n n error (%) n n error (%) 110 2 86 +0.31 2 88 C0.25 150 1 255 0 2 64 +0.16 300 1 127 0 1 129 +0.16 600 0 255 0 1 64 +0.16 1200 0 127 0 0 129 +0.16 2400 0 63 0 0 64 +0.16 4800 0 31 0 0 32 C1.36 9600 0 15 0 0 15 +1.73 19200 0 7 0 0 7 +1.73 31250 0 4 C1.70 0 4 0 38400 0 3 0 0 3 +1.73 notes: 1. settings should be made so that error is within 1%. 2. brr setting values are derived by the following equation. n = 10 6 ?1 osc 64 2 2n b b: bit rate (bits/s) n: brr baud rate generator setting (0 n 255) osc: value of f osc (mhz) n: baud rate generator input clock number (n = 0, 1, 2, 3) 3. the error values in table 10.8 were derived by performing the following calculation and rounding off to two decimal places. error (%) = 100 b ?r r b: bit rate found from n, n, and osc r: bit rate listed in left column of table 10.8 264 the meaning of n is shown in table 10.9. table 10.9 relation between n and clock smr setting n clock cks1 cks0 0 f 00 1 f /4 0 1 2 f /16 1 0 3 f /64 1 1 table 10.10 shows the maximum bit rate for selected frequencies in asynchronous mode. values in table 10.10 are for active (high-speed) mode. table 10.10 maximum bit rate at selected frequencies (asynchronous mode) setting osc (mhz) maximum bit rate (bits/s) n n 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 4.194304 65536 0 0 4.9152 76800 0 0 6 93750 0 0 7.3728 115200 0 0 8 125000 0 0 9.8304 153600 0 0 10 156250 0 0 265 table 10.11 shows typical brr settings in synchronous mode. values in table 10.11 are for active (high-speed) mode. table 10.11 typical brr settings and bit rates (synchronous mode) osc (mhz) bit rate 24810 (bits/s) n n n n n n n n 110 250 1 249 2 124 2 249 500 1 124 1 249 2 124 1k 0 249 1 124 1 249 2.5k 0 99 0 199 1 99 1 124 5k 0 49 0 99 0 199 0 249 10k 0 24 0 49 0 99 0 124 25k 0 9 0 19 0 39 0 49 50k 0 4 0 9 0 19 0 24 100k 0 4 0 9 250k 0 0 * 01 03 04 500k 0 0 * 01 1m 0 0 * 2.5m note: blank: cannot be set : can be set, but error will result * : continuous transfer not possible at this setting brr setting values are derived by the following equation. n = 10 6 ?1 osc 8 2 2n b b: bit rate (bits/s) n: brr baud rate generator setting (0 n 255) osc: value of f osc (mhz) n: baud rate generator input clock number (n = 0, 1, 2, 3) 266 the meaning of n is shown in table 10.12. table 10.12 relation between n and clock smr setting n clock cks1 cks0 0 f 00 1 f /4 0 1 2 f /16 1 0 3 f /64 1 1 10.4.3 operation sci3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses. the choice of asynchronous mode or synchronous mode, and the communication format, is made in the serial mode register (smr), as shown in table 10.13. the sci3 clock source is determined by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3), as shown in table 10.14. asynchronous mode: data length: choice of 7 bits or 8 bits transmit/receive format options include addition of parity bit, multiprocessor bit, and one or two stop bits (character length depends on this combination of options). framing error (fer), parity error (per), overrun error (oer), and line breaks can be detected when data is received. clock source: choice of internal clocks or an external clock when an internal clock is selected: operates on baud rate generator clock. a clock can be output with the same frequency as the bit rate. when an external clock is selected: a clock input with a frequency 16 times the bit rate is required (internal baud rate generator is not used). 267 synchronous mode: transfer format: 8 bits overrun error can be detected when data is received. clock source: choice of internal clocks or an external clock when an internal clock is selected: operates on baud rate generator clock, and outputs a serial clock. when an external clock is selected: the internal baud rate generator is not used. operation is synchronous with the input clock. table 10.13 smr settings and sci3 communication format smr setting communication format bit 7: com bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length multipro- cessor bit parity bit stop bit length 00000 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 01 * 0 asynchronous 8-bit data yes no 1 bit * 1 mode 2 bits 1 * 0 (multiprocessor 7-bit data 1 bit * 1 format) 2 bits 1 * 0 ** synchronous mode 8-bit data no none note: * dont care 268 table 10.14 smr and scr3 settings and clock source selection smr scr3 transmit/receive clock bit 7: com bit 1: cke1 bit 0: cke0 mode clock source pin sck 3 function 0 0 0 asynchronous internal i/o port (sck 3 function not used) 1 mode outputs clock with same frequency as bit rate 1 0 external clock should be input with frequency 16 times the desired bit rate 1 0 0 synchronous internal outputs a serial clock 10 mode external inputs a serial clock 0 1 1 reserved (illegal settings) 110 111 continuous transmit/receive operation using interrupts: continuous transmit and receive operations are possible with sci3, using the rxi or txi interrupts. table 10.15 explains this use of these interrupts. table 10.15 transmit/receive interrupts interrupt flag interrupt conditions remarks rxi rdrf rie when serial data is received normally and receive data is transferred from rsr to rdr, rdrf is set to 1. if rie is 1 at this time, rxi is enabled and an interrupt occurs. (see figure 10.8 (a).) the rxi interrupt handler routine should read the receive data from rdr and clear rdrf to 0. continuous receiving is possible if these operations are completed before the next data has been completely received in rsr. txi tdre tie when tsr empty (previous trans- mission complete) is detected and the transmit data set in tdr is transferred to tsr, tdre is set to 1. if tie is 1 at this time, txi is enabled and an interrupt occurs. (see figure 10.8 (b).) the txi interrupt handler routine should write the next transmit data to tdr and clear tdre to 0.continuous transmission is possible if these operations are completed before the data transferred to tsr has been completely transmitted. tei tend teie when the last bit of the tsr transmit character has been sent, if tdre is 1, then 1 is set in tend. if teie is 1 at this time, tei is enabled and an interrupt occurs. (see figure 10.8 (c).) tei indicates that, when the last bit of the tsr transmit character was sent, the next transmit data had not been written to tdr. 269 rdr rsr (receiving) rxd pin rdrf = 0 rdr rsr (received and transferred) rxd pin rdrf 1 (rxi requested if rie = 1) ? - figure 10.8 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmitting) txd pin tdre = 0 tdr tsr (transmission complete, next data transferred) txd pin tdre 1 (txi requested if tie = 1) ? figure 10.8 (b) tdre setting and txi interrupt tdr tsr (transmitting) txd pin tend = 0 tdr tsr (transmission end) txd pin tend 1 (tei requested if teie = 1) ? figure 10.8 (c) tend setting and tei interrupt 270 10.4.4 operation in asynchronous mode in asynchronous communication mode, a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each character that is sent. in this way synchronization is achieved for each character as a self-contained unit. sci3 consists of independent transmit and receive modules, giving it the capability of full duplex communication. both the transmit and receive modules have a double-buffer configuration, allowing data to be read or written during communication operations so that data can be transmitted and received continuously. transmit/receive formats figure 10.9 shows the general format for asynchronous serial communication. serial data one unit of data (character or frame) start bit transmit or receive data parity bit (msb) stop bit 1 bit 1 bit or none 1 or 2 bits 7 or 8 bits mark state (lsb) 1 figure 10.9 data format in asynchronous serial communication mode the communication line in asynchronous communication mode normally stays at the high level, in the mark state. sci3 monitors the communication line, and begins serial data communication when it detects a space (low-level signal), which is regarded as a start bit. one character consists of a start bit (low level), transmit/receive data (in lsb-first order: starting with the least significant bit), a parity bit (high or low level), and finally a stop bit (high level), in this order. in asynchronous data receiving, synchronization is with the falling edge of the start bit. sci3 samples data on the 8th pulse of a clock that has 16 times the frequency of the bit rate, so each bit of data is latched at its center. table 10.16 shows the 12 transmit/receive formats formats that can be selected in asynchronous mode. the format is selected in the serial mode register (smr). 271 table 10.16 serial communication formats in asynchronous mode smr settings serial transfer format and frame length chr pe mp stop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 * 1 0 s 8-bit data mpb stop 0 * 1 1 s 8-bit data mpb stop stop 1 * 1 0 s 7-bit data mpb stop 1 * 1 1 s 7-bit data mpb stop stop notation: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit note: * dont care 272 clock the clock source is determined by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3). see table 10.14 for the settings. either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin sck 3 . when an external clock is input at pin sck 3 , it should have a frequency 16 times the desired bit rate. when an internal clock source is used, sck 3 is used as the clock output pin. the clock output has the same frequency as the serial bit rate, and is synchronized as in figure 10.10 so that the rising edge of the clock occurs in the center of each bit of transmit/receive data. serial data 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock figure 10.10 phase relation of output clock and communication data in asynchronous mode (8-bit data, parity bit added, and 2 stop bits) data transmit/receive operations sci3 initialization: before data is sent or received, bits te and re in serial control register 3 (scr3) must be cleared to 0, after which initialization can be performed using the procedure shown in figure 10.11. note: when modifying the operation mode, transfer format or other settings, always be sure to clear bits te and re first. when te is cleared to 0, bit tdre will be set to 1. clearing re does not clear the status flags rdrf, per, fer, or oer, or alter the contents of the receive data register (rdr). when an external clock is used in asynchronous mode, do not stop the clock during operation, including during initialization. when an external clock is used in synchronous mode, do not supply the clock during initialization. 273 figure 10.11 shows a typical flow chart for sci3 initialization. start clear te and re to 0 in scr3 select communication format in smr set brr value has a 1-bit interval elapsed? set bits rie, tie, teie, and mpie in scr3, and set te or re to 1 2 3 4 1. 2. 3. 4. select the clock in serial control register 3 (scr3). other bits must be cleared to 0. if clock output is selected in asynchronous mode, a clock signal will be output as soon as cke1 and cke2 have been set. during reception in synchronous mode, if clock output is selected by bits cke1 and cke0, a clock signal will be output as soon as re is set to 1. set the transmit/receive format in the serial mode register (smr). set the bit rate register (brr) to the value giving the desired bit rate. this step is not required when an external clock source is used. wait for at least a 1-bit interval, then set bits rie, tie, teie, and mpie, and set bit te or re in scr3 to 1. setting te or re enables sci3 to use the txd or rxd pin. the initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). no yes wait end 1 set bits cke1 and cke0 figure 10.11 typical flow chart when sci3 is initialized 274 transmitting: figure 10.12 shows a typical flow chart for data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? write transmit data in tdr continue data transmission? tend = 1? read bit tend in ssr break output? set pdr = 0 and pcr = 1 clear bit te in scr3 to 0 end 1 2 3 1. 2. 3. read the serial status register (srr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. to continue transmitting data, read bit tdre to make sure it is set to 1, then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. to output a break signal when transmission ends, first set the port values pcr = 1 and pdr = 0, then clear bit te in scr3 to 0. no yes no no yes no yes yes figure 10.12 typical data transmission flow chart (asynchronous mode) sci3 operates as follows during data transmission. 275 sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. serial data is transmitted from pin txd using the communication format outlined in table 10.16. next, tdre is checked as the stop bit is being transmitted. if tdre is 0, data is transferred from tdr to tsr, and after the stop bit is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the stop bit is sent the output remains at 1 (mark state). a tei interrupt is requested in this state if bit teie in scr3 is set to 1. figure 10.13 shows a typical operation in asynchronous transmission mode. 0 d0 d1 d7 0/1 1 d0 d1 d7 0/1 1 0 start bit parity bit stop bit parity bit stop bit 1 start bit mark state tdre tend txi request tei request 1 frame txi request serial data transmit data transmit data 1 frame sci3 operation user processing tdre cleared to 0 1 write data in tdr figure 10.13 typical transmit operation in asynchronous mode (8-bit data, parity bit added, and 1 stop bit) receiving: figure 10.14 shows a typical flow chart for receiving serial data. after sci3 initialization, follow the procedure below. 276 start read bits oer, per, and fer in ssr read bit rdrf in ssr continue receiving? clear bit re in scr3 to 0 end 1 yes yes no no 1. read bits oer, per, and fer in the serial status register (ssr) to determine if a receive error has occurred. if a receive error has occurred, receive error processing is executed. oer = 1? fer = 1? per = 1? clear bits oer, per, and fer in ssr to 0 overrun error processing break? framing error processing parity error processing yes yes yes no no no yes no 4 receive error processing end receive error processing 4 a start receive error processing a oer + per + fer = 1 rdrf = 1? no yes 2. read the serial status register (ssr), and after confirming that bit rdrf = 1, read received data from the receive data register (rdr). when rdr data is read, rdrf is automatically cleared to 0. 3. to continue receiving data, read bit rdrf and finish reading rdr before the stop bit of the present frame is received. when data is read from rdr, rdrf is automatically cleared to 0. 4. when a receive error occurs, read bits oer, per, and fer in ssr to determine which error (s) occurred. after the necessary error processing, be sure to clear the above bits all to 0. data receiving cannot be resumed while any of bits oer, per, or fer is set to 1. when a framing error occurs, a break can be detected by reading the rxd pin value. 2 read received data in rdr 3 figure 10.14 typical serial data receiving flow chart in asynchronous mode 277 sci3 operates as follows when receiving serial data in asynchronous mode. sci3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. the communication format for data receiving is as outlined in table 10.16. received data is set in rsr from lsb to msb, then the parity bit and stop bit(s) are received. after receiving the data, sci3 performs the following checks: parity check: the number of 1s received is checked to see if it matches the odd or even parity selected in bit pm of smr. stop bit check: the stop bit is checked for a value of 1. if there are two stop bits, only the first bit is checked. status check: the rdrf bit is checked for a value of 0 to make sure received data can be transferred from rsr to rdr. if no receive error is detected by the above checks, bit rdrf is set to 1 and the received data is stored in rdr. at that time, if bit rie in scr3 is set to 1, an rxi interrupt is requested. if the error check detects a receive error, the appropriate error flag (oer, per, or fer) is set to 1. rdrf retains the same value as before the data was received. if at this time bit rie in scr3 is set to 1, an eri interrupt is requested. table 10.17 gives the receive error detection conditions and the processing of received data in each case. note: data receiving cannot be continued while a receive error flag is set. before continuing the receive operation it is necessary to clear the oer, fer, per, and rdrf flags to 0. table 10.17 receive error conditions and received data processing receive error abbrev. detection conditions received data processing overrun error oer receiving of the next data ends while bit rdrf in ssr is still set to 1 received data is not transferred from rsr to rdr framing error fer stop bit is 0 received data is transferred from rsr to rdr parity error per received data does not match the parity (odd/even) set in smr received data is not transferred from rsr to rdr 278 figure 10.15 shows a typical sci3 data receive operation in asynchronous mode. 0 d0 d1 d7 0/1 1 d0 d1 d7 0/1 0 0 start bit parity bit stop bit parity bit stop bit 1 start bit mark (idle state) rdrf fer 1 frame serial data rxi request detects stop bit = 0 eri request due to framing error 1 frame 1 sci3 operation receive data receive data read rdr data user processing rdrf cleared to 0 framing error handling figure 10.15 typical receive operation in asynchronous mode (8-bit data, parity bit added, and 1 stop bit) 10.4.5 operation in synchronous mode in synchronous mode, data is sent or received in synchronization with clock pulses. this mode is suited to high-speed serial communication. sci3 consists of independent transmit and receive modules, so full duplex communication is possible, sharing the same clock between both modules. both the transmit and receive modules have a double-buffer configuration. this allows data to be written during a transmit operation so that data can be transmitted continuously, and enables data to be read during a receive operation so that data can be received continuously. 279 transmit/receive format figure 10.16 shows the general communication data format for synchronous communication. note: * at high level except during continuous transmit/receive. serial data serial clock one unit of communication data (character or frame) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 don't care don't care * * lsb msb 8 bits figure 10.16 data format in synchronous communication mode in synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. data is guaranteed valid at the rising edge of the serial clock. one character of data starts from the lsb and ends with the msb. the communication line retains the msb state after the msb is output. in synchronous receive mode, sci3 latches receive data in synchronization with the rising edge of the serial clock. the transmit/receive format is fixed at 8-bit data. no parity bit or multiprocessor bit is added in this mode. clock either an internal clock from the built-in baud rate generator is used, or an external clock is input at pin sck 3 . the choice of clock sources is designated by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3). see table 10.14 for details on selecting the clock source. when operation is based on an internal clock, a serial clock is output at pin sck 3 . eight clock pulses are output per character of transmit/receive data. when no transmit or receive operation is being performed, the pin is held at the high level. 280 data transmit/receive operations sci3 initialization: before transmitting or receiving data, follow the sci3 initialization procedure explained under 10.4.4, sci3 initialization, and illustrated in figure 10.10. transmitting: figure 10.17 shows a typical flow chart for data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? write transmit data in tdr continue data transmission? read bit tend in ssr tend = 1? write 0 to bit te in scr3 end no yes no yes no yes 1 2 1. 2. read the serial status register (ssr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0 and data transmission begins. if clock output has been selected, after data is written to tdr, the clock is output and data transmission begins. to continue transmitting data, read bit tdre to make sure it is set to 1, then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. figure 10.17 typical data transmission flow chart in synchronous mode 281 sci3 operates as follows during data transmission in synchronous mode. sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. if clock output is selected, sci3 outputs eight serial clock pulses. if an external clock is used, data is output in synchronization with the clock input. serial data is transmitted from pin txd in order from lsb (bit 0) to msb (bit 7). then tdre is checked as the msb (bit 7) is being transmitted. if tdre is 0, data is transferred from tdr to tsr, and after the msb (bit 7) is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the msb (bit 7) has been sent, the msb state is maintained. a tei interrupt is requested in this state if bit teie in scr3 is set to 1. after data transmission ends, pin sck 3 is held at the high level. note: data transmission cannot take place while any of the receive error flags (oer, fer, per) is set to 1. be sure to confirm that these error flags are cleared to 0 before starting transmission. figure 10.18 shows a typical sci3 transmit operation in synchronous mode. serial clock serial data tdre tend bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 bit 1 txi request tdre cleared to 0 txi request tei request 1 frame 1 frame sci3 operation user processing write data in tdr figure 10.18 typical sci3 transmit operation in synchronous mode 282 receiving: figure 10.19 shows a typical flow chart for receiving data. after sci3 initialization, follow the procedure below. start read bit oer in ssr read bit rdrf in ssr read received data in rdr oer = 1? continue receiving? clear bit re in scr3 to 0 end clear bit oer in ssr to 0 1 3 4 4 2. 3. 4. read the serial status register (ssr), and after confirming that bit rdrf = 1, read received data from the receive data register (rdr). when data is read from rdr, rdrf is automatically cleared to 0. 1. read bit oer in the serial status register (ssr) to determine if an error has occurred. if an overrun error has occurred, overrun error processing is executed. to continue receiving data, read bit rdrf and read the received data in rdr before the msb (bit 7) of the present frame is received. when data is read from rdr, rdrf is automatically cleared to 0. when an overrun error occurs, read bit oer in ssr. after the necessary error processing, be sure to clear oer to 0. data receiving cannot be resumed while bit oer is set to 1. yes yes no no rdrf = 1? no yes overrun error processing start overrun processing end overrun error processing overrun error processing 2 figure 10.19 typical data receiving flow chart in synchronous mode 283 sci3 operates as follows when receiving serial data in synchronous mode. sci3 synchronizes internally with the input or output of the serial clock and starts receiving. received data is set in rsr from lsb to msb. after data has been received, sci3 checks to confirm that the value of bit rdrf is 0 indicating that received data can be transferred from rsr to rdr. if this check passes, rdrf is set to 1 and the received data is stored in rdr. at this time, if bit rie in scr3 is set to 1, an rxi interrupt is requested. if an overrun error is detected, oer is set to 1 and rdrf remains set to 1. then if bit rie in scr3 is set to 1, an eri interrupt is requested. for the overrun error detection conditions and receive data processing, see table 10.17. note: data receiving cannot be continued while a receive error flag is set. before continuing the receive operation it is necessary to clear the oer, fer, per, and rdrf flags to 0. figure 10.20 shows a typical receive operation in synchronous mode. serial clock serial data rdrf oer sci3 operation user processing bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 1 frame 1 frame rxi request rdrf cleared to 0 rxi request read data from rdr eri request due to overrun error rdr data not read (rdrf = 1) overrun error handling figure 10.20 typical receive operation in synchronous mode 284 simultaneous transmit/receive: figure 10.21 shows a typical flow chart for transmitting and receiving simultaneously. after sci3 synchronization, follow the procedure below. start read bit tdre in ssr read rdrf in ssr rdrf = 1? read received data in rdr read bit oer in ssr oer = 1? continue transmitting and receiving? clear bits te and re in scr3 to 0 end 1 1. 2. 3. 4. 4 read the serial status register (ssr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. read the serial status register (ssr), and after confirming that bit rdrf = 1, read the received data from the receive data register (rdr). when data is read from rdr, rdrf is automatically cleared to 0. to continue transmitting and receiving serial data, read bit rdrf and finish reading rdr before the msb (bit 7) of the present frame is received. also read bit tdre, check that it is set to 1, and write the next data in tdr before the msb of the current frame has been transmitted. when data is written to tdr, tdre is automatically cleared to 0; and when data is read from rdr, rdrf is automatically cleared to 0. when an overrun error occurs, read bit oer in ssr. after the necessary error processing, be sure to clear oer to 0. data transmission and reception cannot take place while bit oer is set to 1. see figure 10.19 for overrun error processing. tdre = 1? no no yes yes yes no 3 no yes write transmit data in tdr overrun error processing 2 figure 10.21 simultaneous transmit/receive flow chart in synchronous mode 285 notes: 1. to switch from transmitting to simultaneous transmitting and receiving, use the following procedure. ? first confirm that tdre and tend are both set to 1 and that sci3 has finished transmitting. next clear te to 0. then set both te and re to 1. 2. to switch from receiving to simultaneous transmitting and rceiving, use the following procedure. ? after confirming that sci3 has finished receiving, clear re to 0. next, after confirming that rdrf and the error flags (oer fer, per) are all 0, set both te and re to 1. 10.4.6 multiprocessor communication function the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id code. a serial communication cycle consists of two cycles: an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the id-sending cycle and data-sending cycle are differentiated by the multiprocessor bit. the multiprocessor bit is 1 in an id-sending cycle, and 0 in a data-sending cycle. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. when a receiving processor receives data with the multiprocessor bit set to 1, it compares the data with its own id. if the data matches its id, the receiving processor continues to receive incoming data. if the data does not match its id, the receiving processor skips further incoming data until it again receives data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 10.22 shows an example of communication among different processors using a multiprocessor format. 286 transmitting processor receiving processor a communication line receiving processor b receiving processor c receiving processor d serial data id-sending cycle (receiving processor address) data-sending cycle (data sent to receiving processor designated by id) (id = 01) (id = 02) (id = 03) (id = 04) h'01 h'aa (mpb = 1) (mpb = 0) mpb: multiprocessor bit figure 10.22 example of interprocessor communication using multiprocessor format (data h'aa sent to receiving processor a) four communication formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 10.16. for a description of the clock used in multiprocessor communication, see 10.4.4, operation in asynchronous mode. 287 transmitting multiprocessor data: figure 10.23 shows a typical flow chart for multiprocessor serial data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? set bit mpbt in ssr write transmit data to tdr continue transmitting? read bit tend in ssr tend = 1? break output? set pdr = 0 and pcr = 1 clear bit te in scr3 to 0 end 1 2 3 2. 3. 1. to continue transmitting data, read bit tdre to make sure it is set to 1, then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. to output a break signal at the end of data transmission, first set the port values pcr = 1 and pdr = 0, then clear bit te in scr3 to 0. read the serial status register (ssr), and after confirming that bit tdre = 1, set bit mpbt (multiprocessor bit transmit) in ssr to 0 or 1, then write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. no yes no no yes no yes yes figure 10.23 typical multiprocessor data transmission flow chart 288 sci3 operates as follows during data transmission using a multiprocessor format. sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. serial data is transmitted from pin txd using the communication format outlined in table 10.16. next, tdre is checked as the stop bit is being transmitted. if tdre is 0, data is transferred from tdr to tsr, and after the stop bit is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the stop bit is sent the output remains at 1 (mark state). a tei interrupt is requested in this state if bit teie in scr3 is set to 1. figure 10.24 shows a typical sci3 operation in multiprocessor communication mode. 0d0d1 d7 d0 d1 0 d7 1 0/1 1 0/1 start bit start bit stop bit stop bit mpb mpb 1 tdre tend tdre cleared to 0 txi request tei request 1 frame txi request serial data transmit data transmit data mark state 1 frame sci3 operation user processing write data in tdr 1 figure 10.24 typical multiprocessor format transmit operation (8-bit data, multiprocessor bit added, and 1 stop bit) 289 receiving multiprocessor data: figure 10.25 shows a typical flow chart for receiving data using a multiprocessor format. after sci3 initialization, follow the procedure below. start set bit mpie in scr3 to 1 read bits oer and fer in ssr read bit rdrf in ssr rdrf = 1? read received data in rdr oer + fer = 1? read bits oer and fer in ssr continue receiving? end clear bit re in scr3 to 0 start receive error processing oer = 1? fer = 1? clear bits oer and fer in ssr to 0. overrun error processing break? framing error processing 1 2 1. 2. 4. 5. set bit mpie in serial control register 3 (scr3) to 1. read bits oer and fer in the serial status register (ssr) to determine if an error has occurred. if a receive error has occurred, receive error processing is executed. read ssr, check that bit rdrf = 1, then read received data from the receive data register (rdr). if a receive error occurs, read bits oer and fer in ssr to determine which error occurred. after the necessary error processing, be sure to clear the error flags to 0. serial data transfer cannot take place while bit oer or fer is set to 1. when a framing error occurs, a break can be detected by reading the rxd pin value. no yes yes no yes no yes yes no no yes no error processing read received data in rdr a a end receive error processing own id? no read bit rdrf in ssr 4 oer + fer = 1? yes yes no rdrf = 1? no yes 5 3. read the serial status register (ssr) and confirm that rdrf = 1. if rdrf = 1, read the data in the received data register (rdr) and compare it with the processor s own id. if the received data does not match the id, set bit mpie to 1 again. bit rdrf is automatically cleared to 0 when data in the received data register (rdr) is read. 3 figure 10.25 typical flow chart for receiving serial data using multiprocessor format 290 figure 10.26 gives an example of data reception using a multiprocessor format. 0 d0 d1 d7 1 d0 d1 d7 0 1 10 1 start bit stop bit stop bit start bit receive data (id1) receive data (data 1) mark (idle state) mpie rdrf rdr value rxi request mpie cleared to 0 rdrf cleared to 0 no rxi request rdr state retained (a) data does not match own id 0 d0 d1 d7 1 d0 d1 d7 0 1 10 1 start bit stop bit stop bit start bit receive data (id2) receive data (data 2) mark (idle state) mpb mpb mpb mpb mpie rdrf rdr value id1 (b) data matches own id 1 frame 1 frame 1 frame 1 frame id1 if not own id, set mpie to 1 again sci3 operation user processing rxi request mpie cleared to 0 rdrf cleared to 0 if own id, continue receiving sci3 operation user processing rdrf cleared to 0 read data from rdr and set mpie to 1 again data 2 serial data serial data 1 1 rxi request read data from rdr id2 read data from rdr figure 10.26 example of multiprocessor format receive operation (8-bit data, multiprocessor bit added, and 1 stop bit) 291 10.4.7 interrupts sci3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). all share a common interrupt vector. table 10.18 describes each interrupt. table 10.18 sci3 interrupts interrupt description vector address rxi interrupt request due to receive data register full (rdrf) h'0024 txi interrupt request due to transmit data register empty (tdre) tei interrupt request due to transmit end (tend) eri interrupt request due to receive error (oer, fer, or per) the interrupt requests are enabled and disabled by bits tie and rie of scr3. when bit tdre in ssr is set to 1, txi is requested. when bit tend in ssr is set to 1, tei is requested. these two interrupt requests occur during data transmission. the initial value of bit tdre is 1. accordingly, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before placing transmit data in tdr, txi will be requested even though no transmit data has been readied. likewise, the initial value of bit tend is 1. accordingly, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before placing transmit data in tdr, tei will be requested even though no data has been transmitted. these interrupt features can be used to advantage by programming the interrupt handler to move the transmit data into tdr. when this technique is not used, the interrupt enable bits (tie and teie) should not be set to 1 until after tdr has been loaded with transmit data, to avoid unwanted txi and tei interrupts. when bit rdrf in ssr is set to 1, rxi is requested. when any of ssr bits oer, fer, or per is set to 1, eri is requested. these two interrupt requests occur during the receiving of data. details on interrupts are given in 3.3, interrupts. 292 10.4.8 application notes when using sci3, attention should be paid to the following matters. relation between bit tdre and writing data to tdr: bit tdre in the serial status register (ssr) is a status flag indicating that tdr does not contain new transmit data. tdre is automatically cleared to 0 when data is written to tdr. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr regardless of the status of bit tdre. however, if new data is written to tdr while tdre is cleared to 0, assuming the data held in tdr has not yet been shifted to tsr, it will be lost. for this reason it is advisable to confirm that bit tdre is set to 1 before each write to tdr and not write to tdr more than once without checking tdre in between. operation when multiple receive errors occur at the same time: when two or more receive errors occur at the same time, the status flags in ssr are set as shown in table 10.19. if an overrun error occurs, data is not transferred from rsr to rdr, and receive data is lost. table 10.19 ssr status flag states and transfer of receive data ssr status flags receive error status rdrf * oer fer per (rsr ? rdr) receive data transfer 1100 overrun error 0 0 1 0 o framing error 0 0 0 1 o parity error 1110 overrun error + framing error 1101 overrun error + parity error 0 0 1 1 o framing error + parity error 1111 overrun error + framing error + parity error notation: o: receive data transferred from rsr to rdr : receive data not transferred from rsr to rdr note: * rdrf keeps the same state as before the data was received. however, if due to a late read of received data in one frame an overrun error occurs in the next frame, rdrf is cleared to 0 when rdr is read. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state sci3 continues to receive, so if the fer bit is cleared to 0 it will be set to 1 again. 293 sending a mark or break signal: when te is cleared to 0 the txd pin becomes an i/o port, the level and direction (input or output) of which are determined by the pdr and pcr bits. this feature can be used to place the txd pin in the mark state or send a break signal. to place the serial communication line in the mark (1) state before te is set to 1, set the pdr and pcr bits both to 1. since te is cleared to 0, txd becomes a general output port outputting the value 1. to send a break signal during data transmission, set the pcr bit to 1 and clear the pdr bit to 0, then clear te to 0. when te is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an output port outputting the value 0. receive error flags and transmit operation (sysnchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, sci3 will not start transmitting even if tdre is cleared to 0. be sure to clear the receive error flags to 0 when starting to transmit. note that clearing re to 0 does not clear the receive error flags. receive data sampling timing and receive margin in asynchronous mode: in asynchronous mode sci3 operates on a base clock with 16 times the bit rate frequency. in receiving, sci3 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 10.27. 16 clock cycles 8 clock cycles start bit internal base clock receive data (rxd) synchronization sampling timing data sampling timing 07 15 7 150 d0 d1 0 figure 10.27 receive data sampling timing in asynchronous mode 294 the receive margin in asynchronous mode can therefore be derived from the following equation. m = {(0.5 C 1/2n) C (d C 0.5) / n C (l C 0.5) f} 100% ............................ equation (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0.5 to 1) l: frame length (l = 9 to 12) f: absolute value of clock frequency error in equation (1), if f (absolute value of clock frequency error) = 0 and d (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. when d = 0.5 and f = 0, m = {0.5 C 1/(2 16)} 100% = 46.875% ................................................ equation (2) this value is theoretical. in actual system designs a margin of from 20 to 30 percent should be allowed. relationship between bit rdrf and reading rdr: while sci3 is receiving, it checks the rdrf flag. when a frame of data has been received, if the rdrf flag is cleared to 0, data receiving ends normally. if rdrf is set to 1, an overrun error occurs. rdrf is automatically cleared to 0 when the contents of rdr are read. if rdr is read more than once, the second and later reads will be performed with rdrf cleared to 0. while rdrf is 0, if rdr is read when reception of the next frame is just ending, data from the next frame may be read. this is illustrated in figure 10.28. 295 communica- tion line rdrf rdr frame 1 frame 2 frame 3 data 1 data 2 data 3 data 1 data 2 rdr read rdr read at a , data 1 is read. at b , data 2 is read. a b figure 10.28 relationship between data and rdr read timing to avoid the situation described above, after rdrf is confirmed to be 1, rdr should only be read once and should not be read twice or more. when the same data must be read more than once, the data read the first time should be copied to ram, for example, and the copied data should be used. an alternative is to read rdr but leave a safe margin of time before reception of the next frame is completed. in synchronous mode, all reads of rdr should be completed before bit 7 is received. in asynchronous mode, all reads of rdr should be completed before the stop bit is received. caution on switching of sck 3 function: if pin sck 3 is used as a clock output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( f ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. 1. when an sck 3 function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents sck 3 from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck 3 , the line connected to sck 3 should be pulled up to the v cc level via a resistor, or supplied with output from an external device. 296 2. when an sck 3 function is switched from clock output to general input/output when stopping data transfer, a. issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. b. clear bit com in scr3 to 0 c. clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck 3 . caution on switching txd function: if pin txd is used as a data output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a high level signal for one system clock ( f ) cycle immediately after it is switched. 297 section 11 14-bit pwm 11.1 overview the h8/3834 series is provided with a 14-bit pwm (pulse width modulator) on-chip, which can be used as a d/a converter by connecting a low-pass filter. 11.1.1 features features of the 14-bit pwm are as follows. choice of two conversion periods a conversion period of 3,268/ f , with a minimum modulation width of 2/ f (pwcr0 = 1), or a conversion period of 16,384/ f , with a minimum modulation width of 1/ f (pwcr0 = 0), can be chosen. pulse division method for less ripple 11.1.2 block diagram figure 11.1 shows a block diagram of the 14-bit pwm. internal data bus pwdrl pwdru pwcr pwm waveform generator /2 /4 notation: pwdrl: pwdru: pwcr: pwm data register l pwm data register u pwm control register pwm f f figure 11.1 block diagram of the 14 bit pwm 298 11.1.3 pin configuration table 11.1 shows the output pin assigned to the 14-bit pwm. table 11.1 pin configuration name abbrev. i/o function pwm output pin pwm output pulse-division pwm waveform output 11.1.4 register configuration table 11.2 shows the register configuration of the 14-bit pwm. table 11.2 register configuration name abbrev. r/w initial value address pwm control register pwcr w h'fe h'ffd0 pwm data register u pwdru w h'c0 h'ffd1 pwm data register l pwdrl w h'00 h'ffd2 11.2 register descriptions 11.2.1 pwm control register (pwcr) pwcr is an 8-bit write-only register for input clock selection. upon reset, pwcr is initialized to h'fe. bits 7 to 1reserved bits: bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. bit 0clock select 0 (pwcr0): b i t 0 sel ect s the cl ock suppl i ed to the 14-bi t p wm . this bit is a writ e-onl y bi t ; it i s al ways read as 1. bit 0: pwcr0 description 0 the input clock is f /2 (t f * = 2/ f ). the conversion period is 16,384/ f , with a minimum modulation width of 1/ f . (initial value) 1 the input clock is f /4 (t f * = 4/ f ). the conversion period is 32,768/ f , with a minimum modulation width of 2/ f . note: t f : period of pwm input clock 299 11.2.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value written to pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. when 14-bit data is written to pwdru and pwdrl, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 14-bit data should always be written in the following sequence, first to pwdrl and then to pwdru. 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. pwdru and pwdrl are write-only registers. if they are read, all bits are read as 1. upon reset, pwdru and pwdrl are initialized to h'c000. 11.3 operation when using the 14-bit pwm, set the registers in the following sequence. 1. set bit pwm in port mode register 1 (pmr1) to 1 so that pin p1 4 /pwm is designated for pwm output. 2. set bit pwcr0 in the pwm control register (pwcr) to select a conversion period of either 32,768/ f (pwcr0 = 1) or 16,384/ f (pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru/l). be sure to write in the correct sequence, first pwdrl then pwdru. when data is written to pwdru, the data in these registers will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 11.2. the total of the high- level pulse widths during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be represented as follows. t h = (data value in pwdru and pwdrl + 64) t f /2 where t f is the pwm input clock period, either 2/ f (bit pwcr0 = 0) or 4/ f (bit pwcr0 = 1). example: settings in order to obtain a conversion period of 8,192 s: when bit pwcr0 = 0, the conversion period is 16,384/ f , so f must be 2 mhz. in this case t fn = 128 s, with 1/ f (resolution) = 0.5 s. when bit pwcr0 = 1, the conversion period is 32,768/ f , so f must be 4 mhz. in this case t fn = 128 s, with 2/ f (resolution) = 0.5 s. 300 accordingly, for a conversion period of 8,192 s, the system clock frequency ( f ) must be 2 mhz or 4 mhz. 1 conversion period t f1 t f2 t f63 t f64 t h1 t h2 t h3 t h63 t h64 t = t + t + t + t = t = t h h1 h2 h3 h64 ..... t f1 f2 f3 ..... = t f84 figure 11.2 pwm output waveform 301 section 12 a/d converter 12.1 overview the h8/3834 series includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to 12 channels of analog input. 12.1.1 features the a/d converter has the following features. 8-bit resolution 12 input channels conversion time: approx. 12.4 s per channel (at 5 mhz operation) built-in sample-and-hold function interrupt requested on completion of a/d conversion a/d conversion can be started by external trigger input 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus a/d mode register a/d start register a/d result register control logic + C com- parator an an an an an an an an an an an an adtrg av av cc ss multiplexer reference voltage irrad av cc av ss 0 1 2 3 4 5 6 7 8 9 10 11 figure 12.1 block diagram of the a/d converter 302 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbrev. i/o function analog power supply pin av cc input power supply and reference voltage of analog part analog ground pin av ss input ground and reference voltage of analog part analog input pin 0 an 0 input analog input channel 0 analog input pin 1 an 1 input analog input channel 1 analog input pin 2 an 2 input analog input channel 2 analog input pin 3 an 3 input analog input channel 3 analog input pin 4 an 4 input analog input channel 4 analog input pin 5 an 5 input analog input channel 5 analog input pin 6 an 6 input analog input channel 6 analog input pin 7 an 7 input analog input channel 7 analog input pin 8 an 8 input analog input channel 8 analog input pin 9 an 9 input analog input channel 9 analog input pin 10 an 10 input analog input channel 10 analog input pin 11 an 11 input analog input channel 11 external trigger input pin adtrg input external trigger input for starting a/d conversion 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'30 h'ffc4 a/d start register adsr r/w h'7f h'ffc6 a/d result register adrr r not fixed h'ffc5 303 12.2 register descriptions 12.2.1 a/d result register (adrr) bit 76543210 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 initial value read/write rrrrrrrr the a/d result register (adrr) is an 8-bit read-only register for holding the results of analog-to- digital conversion. adrr can be read by the cpu at any time, but the adrr values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored in adrr as 8-bit data; this data is held in adrr until the next conversion operation starts. adrr is not cleared on reset. 12.2.2 a/d mode register (amr) bit 76543210 cks trge ch3 ch2 ch1 ch0 initial value 00110000 read/write r/w r/w r/w r/w r/w r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30. 304 bit 7clock select (cks): bit 7 sets the a/d conversion speed. conversion time bit 7: cks conversion period f = 2 mhz f = 5 mhz 0 62/ f (initial value) 31 s 12.4 s 1 31/ f 15.5 s * note: * operation is not guaranteed if the conversion time is less than 12.4 s. set bit 7 for a value of at least 12.4 s. bit 6external trigger select (trge): bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6: trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit integ4 of the irq edge select register (iegr). see 3.3.2, interrupt edge select register (iegr), for details. bits 5 and 4reserved bits: bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. bits 3 to 0channel select (ch3 to ch0): bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. 305 bit 3: ch3 bit 2: ch2 bit 1: ch1 bit 0: ch0 analog input channel 00 ** no channel selected (initial value) 100an 0 1an 1 10an 2 1an 3 1000an 4 1an 5 10an 6 1an 7 100an 8 1an 9 10an 10 1an 11 note: * dont care 12.2.3 a/d start register (adsr) bit 76543210 adsf initial value 01111111 read/write r/w the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in the a/d result register (adrr), and at the same time adsf is cleared to 0. 306 bit 7a/d start flag (adsf): bit 7 controls and indicates the start and end of a/d conversion. bit 7: adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion bits 6 to 0reserved bits: bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 8-bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit irq4 in port mode register 2 (pmr2) is set to 1, and bit trge in amr is set to 1. then when the input signal edge designated in bit ieg4 of the irq edge select register (iegr) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12.2 shows the timing. 307 f pin adtrg (when bit ieg4 = 0) adsf a/d conversion figure 12.2 external trigger input timing 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.3 shows the operation timing. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an 1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored in the a/d result register (adrr). at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. bit ienad = 1, so an a/d conversion end interrupt is requested. the a/d interrupt handling routine starts. the a/d conversion result is read and processed. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 12.4 and 12.5 show flow charts of procedures for using the a/d converter. 308 idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an 1 ) operation state adrr set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: * ( ) indicates instruction execution by software. figure 12.3 typical a/d converter operation timing 309 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrr data figure 12.4 flow chart of procedure for using a/d converter (1) (polling by software) 310 start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrr data perform a/d conversion? figure 12.5 flow chart of procedure for using a/d converter (2) (interrupts used) 12.6 application notes data in the a/d result register (adrr) should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. 311 section 13 lcd controller/driver 13.1 overview the h8/3834 series has an on-chip segment-type lcd controller circuit, lcd driver, and power supply circuit, for direct driving of an lcd panel. 13.1.1 features features of the lcd controller/driver are as follows. display capacity duty internal driver external segment expansion driver on-chip driver only 40 segments 0 use with external segment expansion driver static 36 segments 476 segments 1/2 36 segments 220 segments 1/3 36 segments 92 segments 1/4 36 segments 92 segments the hd66100 can be used for external expansion of the number of segments. lcd ram capacity 8 bits 64 bytes (512 bits) word access to lcd ram segment output pins can be switched to general-purpose ports in groups of 4 unused common output pins can be used either for boosting common output (by parallel connection) or as ports. displays in all operation modes except standby mode. choice of 11 frame frequencies internal voltage divider for liquid crystal driver power supply 312 13.1.2 block diagram figure 13.1 shows a block diagram of the lcd controller/driver. notation: lpcr: lcr: lcd port control register lcd control register 40-bit shift register segment driver common data latch common driver display timing generator lcd ram 64 bytes lcd driver power supply lpcr lcr internal data bus v v v v v cc 1 2 3 ss com com 1 4 seg /cl seg /cl seg /do seg /m seg 40 39 38 37 36 1 2 seg 1 m cl 1 seg , do n cl 2 /2 to /256 to w /4 w ff ff figure 13.1 lcd controller/driver block diagram 313 13.1.3 pin configuration table 13.1 shows the output pins assigned to the lcd controller/driver. table 13.1 pin configuration name abbrev. i/o function lcd segment output seg 40 to seg 1 output liquid crystal segment driver pins. all pins can be programmed also as ports. lcd common output com 4 to output liquid crystal common driver pins. parallel com 1 connection is possible at static and 1/2 duty. external segment cl 1 output display data latch clock; doubles as seg 40 expansion signal cl 2 output display data shift clock; doubles as seg 39 m output lcd alternating signal; doubles as seg 37 do output serial display data; doubles as seg 38 lcd power supply v 1 , v 2 , v 3 input for external connection to bypass capacitor or for use of external power supply circuit 13.1.4 register configuration table 13.2 shows the register configuration of the lcd controller/driver. table 13.2 register configuration name abbrev. r/w initial value address lcd port control register lpcr r/w h'00 h'ffc0 lcd control register lcr r/w h'80 h'ffc1 lcd ram r/w not fixed h'f740 to h'f77f * note: * value after reset. 314 13.2 register descriptions 13.2.1 lcd port control register (lpcr) the lcd port control register is an 8-bit read/write register, used for selecting the duty cycle and the lcd driver and pin functions, etc. upon reset, lpcr is initialized to h'00. bits 7 to 5duty and common function select (dts1, dts0, cmx): bits 7 to 6 select a driver duty of static, 1/2, 1/3, or 1/4. bit 5 determines whether the common pins not used at a given duty are to be used as ports or, in order to increase the common driving capacity, as multiple pins outputting the same waveform. bit 7: dts1 bit 6: dts0 bit 5: cmx duty common driver * 1 other uses 0 0 0 static com 1 (initial value) com 4 , com 3 and com 2 usable as ports 1 com 4 to com 1 com 4 , com 3 and com 2 output the same waveform as com 1 0 1 0 1/2 duty com 2 to com 1 com 4 and com 3 usable as ports 1 com 4 to com 1 com 4 outputs the same waveform as com 3 , and com 2 the same waveform as com 1 1 0 0 1/3 duty com 3 to com 1 com 4 usable as port 1 com 4 to com 1 com 4 outputs a non-select waveform * 2 1 1 0 1/4 duty com 4 to com 1 1 notes: 1. pins com 4 to com 1 become ports when bit sgx = 0 and bits sgs3 to sgs0 = 0000. otherwise the common drivers are as indicated in the table above. 2. a non-select waveform is always output at pin com 4 , which therefore should not be used. bit 4expansion signal select (sgx): bit 4 selects whether pins seg 40 /cl 1 , seg 39 /cl 2 , seg 38 /do, and seg 37 /m are used as segment pins (seg 40 to seg 37 ) or as external segment expansion pins (cl 1 , cl 2 , do, m). bit 4: sgx description 0 pins seg 40 to seg 37 * (initial value) 1 pins cl 1 , cl 2 , do, m note: * selected as ports when bits sgs3 to sgs0 = 0000. bits 3 to 0segment driver select (sgs3 to sgs0): bits 3 to 0 select the pins to be used as segment drivers. 315 functions of pins seg 40 to seg 21 bit 4: sgx bit 3: sgs3 bit 2: sgs2 bit 1: sgs1 bit 0: sgs0 seg 40 to seg 37 seg 36 to seg 33 seg 32 to seg 29 seg 28 to seg 25 seg 24 to seg 21 remarks 00000 port port port port port (initial value) 0001 segseg port port port 0010 segsegseg port port 0011 segsegsegseg port 0100 segsegsegsegseg 0101 segsegsegsegseg 0110 segsegsegsegseg 0111 segsegsegsegseg 1 ** 0 seg seg seg seg seg 1 ** 1 seg seg seg seg seg 10000 external segment expansion port port port port 0001 external segment expansion seg port port port 0010 external segment expansion seg seg port port 0011 external segment expansion seg seg seg port 0100 external segment expansion seg seg seg seg 0101 external segment expansion seg seg seg seg 0110 external segment expansion seg seg seg seg 0111 external segment expansion seg seg seg seg 1 ** 0 external segment expansion seg seg seg seg 1 ** 1 external segment expansion seg seg seg seg note: * dont care 316 functions of pins seg 20 to seg 1 bit 4: sgx bit 3: sgs3 bit 2: sgs2 bit 1: sgs1 bit 0: sgs0 seg 20 to seg 17 seg 16 to seg 13 seg 12 to seg 9 seg 8 to seg 5 seg 4 to seg 1 remarks 00000 port port port port port (initial value) 0001 port port port port port 0010 port port port port port 0011 port port port port port 0100 port port port port port 0101 seg port port port port 0110 segseg port port port 0111 segsegseg port port 1 ** 0 seg seg seg seg port 1 ** 1 seg seg seg seg seg 10000 port port port port port 0001 port port port port port 0010 port port port port port 0011 port port port port port 0100 port port port port port 0101 seg port port port port 0110 segseg port port port 0111 segsegseg port port 1 ** 0 seg seg seg seg port 1 ** 1 seg seg seg seg seg note: * dont care 13.2.2 lcd control register (lcr) bit 76543210 psw act disp cks3 cks2 cks1 cks0 initial value 10000000 read/write r/w r/w r/w r/w r/w r/w r/w the lcd control register is an 8-bit read/write register for on/off control of the resistive voltage divider used as the lcd driver power supply, for display data control, and for frame frequency selection. upon reset, lcr is initialized to h'80. bit 7reserved bit: bit 7 is reserved; it is always read as 1, and cannot be modified. 317 bit 6power switch (psw): bit 6 switches the resistive voltage divider provided to power the lcd driver on/off. in low-power modes when the lcd display is not used, or when an external power supply is used for the lcd, the resistive voltage divider can be switched off. when bit act = 0, or in standby mode, the resistive voltage divider is in the off state regardless of the bit 6 setting. bit 6: psw description 0 lcd power supply resistive voltage divider off (initial value) 1 lcd power supply resistive voltage divider on bit 5:display active (act): bit 5 selects whether the lcd controller/driver is used or not. when this bit is cleared to 0, the lcd controller/driver module halts operation, and the resistive voltage divider provided for the lcd driver power supply goes to the off state regardless of the psw setting. however, register contents are retained. bit 5: act description 0 lcd controller/driver operation stopped (initial value) 1 lcd controller/driver operational bit 4display data control (disp): bit 4 selects whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. this bit is valid also when the hd66100 is used for external segment expansion. bit 4: disp description 0 blank data displayed (initial value) 1 lcd ram data displayed bits 3 to 0frame frequency select 3 to 0 (cks3 to cks0): bits 3 to 0 select the clock used by the lcd controller/driver, and the frame frequency. in subactive, watch, and subsleep modes the system clock ( f ) is stopped, so there will be no display in these modes if f /2 to f /256 is chosen as the clock source. for display in these modes, clock f w /2 or f w /4 must be selected. 318 bit 3: bit 2: bit 1: bit 0: frame frequency * 3 cks3 cks2 cks1 cks0 clock f = 5 mhz f = 625 khz * 1 0 * 00 f w 128 hz * 2 128 hz * 2 0 * 01 f w /2 64 hz 64 hz 0 * 1 * f w /4 32 hz 32 hz 1000 f /2 610 hz 1001 f /4 305 hz 1010 f /8 153 hz 1011 f /16 610 hz 76.3 hz 1100 f /32 305 hz 38.1 hz 1101 f /64 153 hz 1110 f /128 76.3 hz 1111 f /256 38.1 hz notes: * dont care 1. frame frequency in active (medium-speed) mode when f = 5 mhz 2. only the upper 32 bytes of the display ram are used. 3. when a duty cycle of 1/3 is chosen, the frame frequency will be 4/3 times the frequencies shown in the above table. 13.3 operation 13.3.1 settings prior to lcd display various decisions related to hardware and software must be made before using the lcd controller/driver with an lcd display. the settings are described below. hardware settings use at 1/2 duty to use at 1/2 duty, connect pins v 2 and v 3 as shown in figure 13.2. 319 v cc v ss v1 v2 v3 figure 13.2 lcd driver power supply processing at 1/2 duty large-panel display because of the large impedance of the built-in resistive voltage divider, the h8/3834 series lcd controller/driver is not well suited to driving large-panel displays. if use of a large panel leads to an unclear display, refer to 13.3.5 boosting the lcd driver power supply. at static and 1/2 duty it is possible to boost the common output driving capacity. set bit cmx to 1 when selecting the duty cycle. in this mode, at static duty pins com 4 to com 1 output the same waveform, while at 1/2 duty pins com 2 and com 1 output the com 1 waveform and pins com 4 and com 3 output the com 2 waveform. segment expansion the hd66100 can be connected externally to expand the number of segments. see 13.3.3, connection to hd66100. software settings duty cycle selection the duty cycle is selected in bits dts1 and dts0, with a choice of static, 1/2, 1/3, or 1/4 duty. segment driver selection the segment drivers to be used are selected in bits sgs3 to sgs0. frame frequency selection the frame frequency is selected in bits cks3 to cks0. the frame frequency should be selected depending on the specification of the lcd panel to be used. refer to 13.3.4, operation in power-down modes, for information on clock selection in watch mode, subactive mode, and subsleep mode. 320 13.3.2 relation of lcd ram to display the relation of the lcd ram to segments depends on the duty cycle. lcd ram memory maps for each duty cycle when segments are not expanded externally are shown in figures 13.3 to 13.6. when segments are expanded externally, the lcd ram memory maps for each duty cycle are as shown in figures 13.7 to 13.10. it is also possible to use only external segments and not use the segment pins on this chip, in which case the lcd ram memory map is as shown in figure 13.11. after setting the registers that control the lcd display, write data to the area corresponding to the duty cycle selected, using the same instructions as for the ordinary ram. if the display is switched on, the data will be displayed automatically. both word and byte access instructions can be used for writing to the lcd ram. 13.3.3 connection to hd66100 to expand the number of segments externally, connect the h8/3834 series to the hd66100 segment chip. the hd66100 chip provides an additional 80 segments. when external segments are used, set bit sgx in lpcr for use of pins seg 40 to seg 37 as external segment expansion signal pins. data will be output starting from lcd ram pin seg 37 . when bits sgs3 to sgs0 in lpcr are set to 0000, data will be output starting from lcd ram pin seg 1 . figure 13.12 shows typical connections to the hd66100. the output level is determined by the combination of data pins and pin m; but that combination differs between the h8/3834 series and the hd66100. table 13.3 shows the output level of the lcd driver power supply. figure 13.13 shows the common and segment waveforms at each duty. if bit act = 0, then if cl 2 = 0, cl 1 = 0 and m = 0, do stops with the data output at that moment (1 or 0). in standby mode the expansion pins are in the high-impedance (floating) state. external expansion increases the load on the lcd panel, as a result of which the internal power supply may not have sufficient capacity. in that case refer to 13.3.5, boosting the lcd driver power supply. 321 internal driver display area area not used for display bit 7 seg seg com bit 6 seg seg com bit 5 seg seg com bit 4 seg seg com bit 3 seg seg com bit 2 seg seg com bit 1 seg seg com bit 0 seg seg com h'f740 * h'f753 * h'f77f * note: * values immediately after reset. 2 40 4 2 40 3 2 40 2 2 40 1 1 39 4 1 39 3 1 39 2 1 39 1 figure 13.3 lcd ram map: no external segment expansion (1/4 duty) internal driver display area area not used for display bit 7 bit 6 seg seg com bit 5 seg seg com bit 4 seg seg com bit 3 bit 2 seg seg com bit 1 seg seg com bit 0 seg seg com h'f740 * h'f753 * h'f77f * note: * values immediately after reset. 2 40 3 2 40 2 2 40 1 1 39 3 1 39 2 1 39 1 figure 13.4 lcd ram map: no external segment expansion (1/3 duty) 322 internal driver display area area not used for display bit 7 seg seg com bit 6 seg seg com bit 5 seg seg com bit 4 seg seg com bit 3 seg seg com bit 2 seg seg com bit 1 seg seg com bit 0 seg seg com h'f740 * h'f749 * h'f77f * note: * values immediately after reset. 4 40 2 4 40 1 3 39 2 3 39 1 2 38 2 2 38 1 1 37 2 1 37 1 figure 13.5 lcd ram map: no external segment expansion (1/2 duty) internal driver display area area not used for display bit 7 seg seg com bit 6 seg seg com bit 5 seg seg com bit 4 seg seg com bit 3 seg seg com bit 1 seg seg com bit 0 seg seg com bit 2 seg seg com h'f740 * h'f744 * h'f77f * note: * values immediately after reset. 8 40 1 7 39 1 6 38 1 5 37 1 4 36 1 3 35 1 2 34 1 1 33 1 figure 13.6 lcd ram map: no external segment expansion (static duty) 323 internal driver display area external driver display area external driver display area (when cks3 = cks1 = cks0 = 0) bit 6 seg seg seg seg seg com bit 5 seg seg seg seg seg com bit 4 seg seg seg seg seg com bit 3 seg seg seg seg seg com bit 2 seg seg seg seg seg com bit 1 seg seg seg seg seg com bit 0 seg seg seg seg seg com bit 7 seg seg seg seg seg com h'f740 * h'f751 * h'f75f * h'f77f * note: * values immediately after reset. 2 36 38 64 128 4 2 36 38 64 128 3 2 36 38 64 128 2 2 36 38 64 128 1 1 35 37 63 127 4 1 35 37 63 127 3 1 35 37 63 127 2 1 35 37 63 127 1 figure 13.7 lcd ram map: external segment expansion (1/4 duty) internal driver display area external driver display area external driver display area (when cks3 = cks1 = cks0 = 0) bit 7 bit 6 seg seg seg seg seg com bit 5 seg seg seg seg seg com bit 4 seg seg seg seg seg com bit 3 bit 2 seg seg seg seg seg com bit 1 seg seg seg seg seg com bit 0 seg seg seg seg seg com h'f740 * h'f751 * h'f75f * h'f77f * note: * values immediately after reset. 2 36 38 64 128 3 2 36 38 64 128 2 2 36 38 64 128 1 1 35 37 63 127 3 1 35 37 63 127 2 1 35 37 63 127 1 figure 13.8 lcd ram map: external segment expansion (1/3 duty) 324 internal driver display area external driver display area external driver display area (when cks3 = cks1 = cks0 = 0) bit 7 seg seg seg seg seg com bit 6 seg seg seg seg seg com bit 5 seg seg seg seg seg com bit 4 seg seg seg seg seg com bit 3 seg seg seg seg seg com bit 2 seg seg seg seg seg com bit 1 seg seg seg seg seg com bit 0 seg seg seg seg seg com h'f740 * h'f748 * h'f75f * h'f77f * note: * values immediately after reset. 4 36 40 128 256 2 4 36 40 128 256 1 3 35 39 127 255 2 3 35 39 127 255 1 2 34 38 126 254 2 2 34 38 126 254 1 1 33 37 125 253 2 1 33 37 125 253 1 figure 13.9 lcd ram map: external segment expansion (1/2 duty) internal driver display area external driver display area external driver display area (when cks3 = cks1 = cks0 = 0) seg seg seg seg seg seg seg seg bit 3 seg seg com bit 2 seg seg com bit 1 seg seg com bit 0 seg seg com bit 7 seg seg com bit 6 seg seg com bit 5 seg seg com bit 4 seg seg com seg seg seg seg seg seg seg seg h'f740 * h'f744 * h'f75f * h'f77f * note: * values immediately after reset. 8 40 256 512 1 7 39 255 511 1 6 38 254 510 1 5 37 253 509 1 4 36 252 508 1 3 35 251 507 1 2 34 250 506 1 1 33 249 505 1 figure 13.10 lcd ram map: external segment expansion (static duty) 325 external driver display area external driver display area (when cks3 = cks1 = cks0 = 0) bit 7 seg seg seg com bit 6 seg seg seg com bit 5 seg seg seg com bit 4 seg seg seg com bit 3 seg seg seg com bit 2 seg seg seg com bit 1 seg seg seg com bit 0 seg seg seg com h'f740 * h'f75f * h'f77f * note: * values immediately after reset. 2 64 128 4 2 64 128 3 2 64 128 2 2 64 128 1 1 63 127 4 1 63 127 3 1 63 127 2 1 63 127 1 figure 13.11 lcd ram map when all external segments are used (example: sgx = 1, sgs3 to sgs0 = 0000, 1/4 duty) 326 v cc v 1 v 2 v 3 v ss seg /cl 1 seg /cl 2 seg /do seg /m h8/3834 v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 1 v 2 v 3 v ss seg /cl 1 seg /cl 2 seg /do seg /m h8/3834 v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 1 v 2 v 3 v ss seg /cl 1 seg /cl 2 seg /do seg /m h8/3834 v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 1/3 bias; 1/4 duty or 1/3 duty 1/2 duty static 40 39 38 37 40 39 38 37 40 39 38 37 figure 13.12 connection to hd66100 327 1 frame m data com com com com seg v v v v v v v v v v v v v v v v v v v v 1 2 3 4 n 1 2 3 ss 1 2 3 ss 1 2 3 ss 1 2 3 ss 1 2 3 ss figure 13.13 (a) waveforms at 1/4 duty 1 frame m data com com com seg v v v v v v v v v v v v v v v v 1 2 3 n 1 2 3 ss 1 2 3 ss 1 2 3 ss 1 2 3 ss figure 13.13 (b) waveforms at 1/3 duty 328 1 frame m data com com seg v v , v v v v , v v 1 2 1 2 3 ss 1 2 3 ss n figure 13.13 (c) waveforms at 1/2 duty 1 frame m data com seg v v v v 1 n 1 ss 1 ss figure 13.13 (d) waveforms at static duty 329 table 13.3 output levels data 0 0 1 1 m 010 1 static common output v 1 v ss v 1 v ss segment output v 1 v ss v ss v 1 1/2 duty common output v 2 , v 3 v 2 , v 3 v 1 v ss segment output v 1 v ss v ss v 1 1/3 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 1/4 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 13.3.4 operation in power-down modes the lcd controller/driver can be operated in the low-power modes, as shown in table 13.4. in the subactive, watch, and subsleep modes, the system clock pulse generator stops running, so no clock signal will be supplied and the display will be stopped, unless f w or f w /2 was selected when setting bits cks3 to cks0 in lcr. since this may result in a direct current being applied to the lcd panel, be sure to select f w or f w /2 as the clock if these modes are used. in active (medium- speed) mode the system clock is changed, making it necessary to adjust the frame frequency setting (in bits cks3 to cks0) to avoid a change in frame frequency. table 13.4 lcd controller/driver operation in power-down modes mode reset active sleep watch subactive subsleep standby clock f running running running stopped stopped stopped stopped f w running running running running running running stopped * 1 display act = 0 stopped stopped stopped stopped stopped stopped stopped * 2 act = 1 stopped on on on * 3 on * 3 on * 3 stopped * 2 notes: 1. the subclock pulse generator does not stop, but clock supply is stopped. 2. the lcd driver power supply resistive voltage divider is off regardless of bit psw. 3. the display will not function unless f w or f w /2 is selected as the clock. 330 13.3.5 boosting the lcd driver power supply when a large lcd panel is driven, or if segments are expanded externally, the built-in power supply capacity may be insufficient, making it necessary to lower the power supply impedance. one method, shown in figure 13.12, is to connect a bypass capacitor of around 0.1 f to 0.3 f to pins v 1 , v 2 , and v 3 . another approach, shown in figure 13.14 below, is to connect a resistive voltage divider externally. v cc v ss v v v h8/3834 r r r r r = several k w c = 0.1 f to 0.3 f m 1 2 3 m figure 13.14 connecting an external resistive voltage divider 331 section 14 electrical characteristics 14.1 h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s and h8/3837s absolute maximum ratings (standard specifications) table 14.1 lists the absolute maximum ratings. table 14.1 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +7.0 v analog power supply voltage av cc C0.3 to +7.0 v input voltage ports other than ports b and c v in C0.3 to v cc + 0.3 v ports b and c av in C0.3 to av cc + 0.3 v operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 332 14.2 h8/3832s, h8/3833s and h8/3834s electrical characteristics (standard specifications) 14.2.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3832s, h8/3833s and h8/3834s are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range of h8/3832s, h8/3833s and h8/3834s 10.0 2.5 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.5 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speed) sleep mode ? all operating modes 5.0 2.0 333 2. power supply voltage vs. clock frequency range of h8/3832s, h8/3833s and h8/3834s 625.0 2.5 4.0 5.5 v (v) cc (khz) 5.0 2.5 4.0 5.5 v (v) cc (mhz) 16.384 2.5 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range of h8/3832s, h8/3833s and h8/3834s 2.5 4.0 5.5 av (v) cc (mhz) 2.5 4.0 5.5 av (v) cc (khz) 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 f f 334 14.2.2 dc characteristics table 14.2 lists the dc characteristics of the h8/3832s, h8/3833s and h8/3834s. table 14.2 dc characteristics of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.9 v cc v cc + 0.3 ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 osc 1 v cc C 0.5 v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc C 0.3 v cc + 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.8 v cc v cc + 0.3 pb 0 to pb 7 0.7 v cc av cc + 0.3 v v cc = 4.0 v to 5.5 v pc 0 to pc 3 0.8 v cc av cc + 0.3 input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.1 v cc ud, si 1 , si 2 , rxd C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v C0.3 0.2 v cc osc 1 C0.3 0.5 v v cc = 4.0 v to 5.5 v C0.3 0.3 note: connect pin test to v ss . 335 table 14.2 dc characteristics of h8/3832s, h8/3833s and h8/3834s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.2 v cc output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma 336 table 14.2 dc characteristics of h8/3832s, h8/3833s and h8/3834s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input leakage current |i il | res osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos Ci p p1 0 to p1 7 p3 0 to p3 7 50.0 300.0 a v cc = 5 v, v in = 0 v current p5 0 to p5 7 p6 0 to p6 7 35.0 a v cc = 2.7 v, v in = 0 v reference value input capaci- tance c in all input pins except power supply 15.0 pf f = 1 mhz, v in = 0 v t a = 25c 337 table 14.2 dc characteristics of h8/3832s, h8/3833s and h8/3834s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 9.0 13.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 1.7 3.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 4.0 7.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 30.0 65.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 22.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 20.0 45.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 watch mode current dissipation i watch v cc 5.5 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator 1, 2 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 338 table 14.2 dc characteristics of h8/3832s, h8/3833s and h8/3834s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 10.0 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 80.0 v cc = 4.0 v to 5.5 v all output pins 20.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v 0.2 allowable output high current (total) s Ci oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v 10.0 339 14.2.3 ac characteristics table 14.3 lists the control signal timing, and tables 14.4 and 14.5 list the serial interface timing of the h8/3832s, h8/3833s and h8/3834s. table 14.3 control signal timing of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock f osc osc 1 , osc 2 2.0 10.0 mhz v cc = 4.0 v to 5.5 v oscillation frequency 2.0 5.0 osc clock ( f osc )t osc osc 1 , osc 2 100.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 cycle time 200.0 1000.0 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization t rc osc 1 , osc 2 40.0 ms v cc = 4.0 v to 5.5 v time (crystal oscillator) 60.0 v cc = 2.7 v to 5.5 v 100.0 oscillation stabilization time t rc x 1 , x 2 2 s external clock high t cph osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock low t cpl osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock rise time t cpr 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 external clock fall time t cpf 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system clock control register 2 (syscr2). 340 table 14.3 control signal timing of h8/3832s, h8/3833s and h8/3834s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure pin res low width t rel res 10 t cyc figure 14.2 input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 341 table 14.4 serial interface (sci1, sci2) timing of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise t sckr sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 input serial clock fall t sckf sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 serial output data t sod so 1 , so 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 delay time 350.0 serial input data t sis si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 setup time 400.0 serial input data t sih si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 hold time 400.0 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 342 table 14.5 serial interface (sci3) timing of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time t txd 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 1 receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 343 14.2.4 a/d converter characteristics table 14.6 shows the a/d converter characteristics of the h8/3832s, h8/3833s and h8/3834s. table 14.6 a/d converter characteristics of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 2.5 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v 3.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v 3.5 lsb conversion 12.4 124 s av cc = 4.5 v to 5.5 v time 24.8 124 s notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 344 14.2.5 lcd characteristics table 14.7 lists the lcd characteristics, and table 14.8 lists the ac characteristics for external segment expansion of the h8/3832s, h8/3833s and h8/3834s. table 14.7 lcd characteristics of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 100.0 300.0 600.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss table 14.8 ac characteristics for external segment expansion of h8/3832s, h8/3833s and h8/3834s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 345 14.3 h8/3835s, h8/3836s and h8/3837s electrical characteristics (standard specifications) 14.3.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3835s, h8/3836s and h8/3837s are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range of h8/3835s, h8/3836s and h8/3837s 10.0 2.5 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.5 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speeds) sleep mode ? all operating modes 5.0 2.0 346 2. power supply voltage vs. clock frequency range of h8/3835s, h8/3836s and h8/3837s 625.0 2.5 4.0 5.5 v (v) cc (khz) 5.0 2.5 4.0 5.5 v (v) cc (mhz) 16.384 2.5 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range of h8/3835s, h8/3836s and h8/3837s 2.5 4.0 5.5 av (v) cc 2.5 4.0 5.5 av (v) cc 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 (mhz) (khz) f f 347 14.3.2 dc characteristics table 14.9 lists the dc characteristics of the h8/3835s, h8/3836s and h8/3837s. table 14.9 dc characteristics of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.9 v cc v cc + 0.3 ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 osc 1 v cc C 0.5 v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc C 0.3 v cc + 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.8 v cc v cc + 0.3 pb 0 to pb 7 0.7 v cc av cc + 0.3 v v cc = 4.0 v to 5.5 v pc 0 to pc 3 0.8 v cc av cc + 0.3 input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.1 v cc ud, si 1 , si 2 , rxd C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v C0.3 0.2 v cc osc 1 C0.3 0.5 v v cc = 4.0 v to 5.5 v C0.3 0.3 note: connect pin test to v ss . 348 table 14.9 dc characteristics of h8/3835s, h8/3836s and h8/3837s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.2 v cc output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma note: connect pin test to v ss . 349 table 14.9 dc characteristics of h8/3835s, h8/3836s and h8/3837s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input leakage current |i il | res osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos Ci p p1 0 to p1 7 p3 0 to p3 7 50.0 300.0 a v cc = 5 v, v in = 0 v current p5 0 to p5 7 p6 0 to p6 7 35.0 a v cc = 2.7 v, v in = 0 v reference value input capaci- tance c in all input pins except power supply 15.0 pf f = 1 mhz, v in = 0 v t a = 25c 350 table 14.9 dc characteristics of h8/3835s, h8/3836s and h8/3837s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 9.0 13.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 1.7 3.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 4.0 7.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 30.0 65.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 22.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 20.0 45.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 watch mode current dissipation i watch v cc 5.5 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator 1, 2 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 351 table 14.9 dc characteristics of h8/3835s, h8/3836s and h8/3837s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 10.0 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 80.0 v cc = 4.0 v to 5.5 v all output pins 20.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v 0.2 allowable output high current (total) s Ci oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v 10.0 352 14.3.3 ac characteristics table 14.10 lists the control signal timing, and tables 14.11 and 14.12 list the serial interface timing of the h8/3835s, h8/3836s and h8/3837s. table 14.10 control signal timing of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock f osc osc 1 , osc 2 2.0 10.0 mhz v cc = 4.0 v to 5.5 v oscillation frequency 2.0 5.0 osc clock ( f osc )t osc osc 1 , osc 2 100.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 cycle time 200.0 1000.0 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization t rc osc 1 , osc 2 40.0 ms v cc = 4.0 v to 5.5 v time (crystal oscillator) 60.0 v cc = 2.7 v to 5.5 v 100.0 oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high t cph osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock low t cpl osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock rise time t cpr 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 external clock fall time t cpf 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system clock control register 2 (syscr2). 353 table 14.10 control signal timing of h8/3835s, h8/3836s and h8/3837s (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure pin res low width t rel res 10 t cyc figure 14.2 input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 354 table 14.11 serial interface (sci1, sci2) timing of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise t sckr sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 input serial clock fall t sckf sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 serial output data t sod so 1 , so 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 delay time 350.0 serial input data t sis si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 setup time 400.0 serial input data t sih si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 hold time 400.0 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 355 table 14.12 serial interface (sci3) timing of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time t txd 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 1 receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 356 14.3.4 a/d converter characteristics table 14.13 shows the a/d converter characteristics of the h8/3835s, h8/3836s and h8/3837s. table 14.13 a/d converter characteristics of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 2.5 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v 3.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v 3.5 lsb conversion 12.4 124 s av cc = 4.5 v to 5.5 v time 24.8 124 s notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 357 14.3.5 lcd characteristics table 14.14 lists the lcd characteristics, and table 14.15 lists the ac characteristics for external segment expansion of the h8/3835s, h8/3836s and h8/3837s. table 14.14 lcd characteristics of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 100.0 300.0 600.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss table 14.15 ac characteristics for external segment expansion of h8/3835s, h8/3836s and h8/3837s v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 358 14.4 h8/3832s, h8/3833s, h8/3834s, h8/3835s, h8/3836s and h8/3837s absolute maximum ratings (wide temperature range (i-spec) version) table 14.6 lists the absolute maximum ratings. table 14.6 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +7.0 v analog power supply voltage av cc C0.3 to +7.0 v input voltage ports other than ports b and c v in C0.3 to v cc + 3.0 v ports b and c av in C0.3 to av cc + 3.0 v operating temperature t opr C40 to +85 c storage temperature t stg C55 to +125 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 359 14.5 h8/3832s, h8/3833s and h8/3834s electrical characteristics (wide temperature range (i-spec) version) 14.5.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range 10.0 2.5 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.5 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speeds) sleep mode ? all operating modes 5.0 2.0 360 2. power supply voltage vs. clock frequency range 625.0 2.5 4.0 5.5 v (v) cc (khz) 5.0 2.5 4.0 5.5 v (v) cc (mhz) 16.384 2.5 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range 2.5 4.0 5.5 av (v) cc 2.5 4.0 5.5 av (v) cc 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 (mhz) (khz) f f 361 14.5.2 dc characteristics table 14.17 lists the dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version). table 14.17 dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.9 v cc v cc + 0.3 ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 osc 1 v cc C 0.5 v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc C 0.3 v cc + 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.8 v cc v cc + 0.3 pb 0 to pb 7 0.7 v cc av cc + 0.3 v v cc = 4.0 v to 5.5 v pc 0 to pc 3 0.8 v cc av cc + 0.3 input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.1 v cc ud, si 1 , si 2 , rxd C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v C0.3 0.2 v cc note: connect pin test to v ss . 362 table 14.17 dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low v il osc 1 C0.3 0.5 v v cc = 4.0 v to 5.5 v voltage C0.3 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.2 v cc output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma 363 table 14.17 dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note output low voltage v ol p2 0 to p2 7 p3 0 to p3 7 1.5 v v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma input/ output leakage current |i il | res osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos Ci p p1 0 to p1 7 p3 0 to p3 7 50.0 300.0 a v cc = 5 v, v in = 0 v current p5 0 to p5 7 p6 0 to p6 7 35.0 a v cc = 2.7 v, v in = 0 v reference value input capaci- tance c in all input pins except power supply 15.0 pf f = 1 mhz, v in = 0 v t a = 25c 364 table 14.17 dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 9.0 13.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 1.7 3.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 4.0 7.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 30.0 65.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 22.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 20.0 45.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 watch mode current dissipation i watch v cc 5.5 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator 1, 2 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 365 table 14.17 dc characteristics of h8/3832s, h8/3833s and h8/3834s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 10.0 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 80.0 v cc = 4.0 v to 5.5 v all output pins 20.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v 0.2 allowable output high current (total) s Ci oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v 10.0 366 14.5.3 ac characteristics table 14.18 lists the control signal timing, and tables 14.19 and 14.20 list the serial interface timing of the h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version). table 14.18 control signal timing of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock f osc osc 1 , osc 2 2.0 10.0 mhz v cc = 4.0 v to 5.5 v oscillation frequency 2.0 5.0 osc clock ( f osc )t osc osc 1 , osc 2 100.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 cycle time 200.0 1000.0 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization t rc osc 1 , osc 2 40.0 ms v cc = 4.0 v to 5.5 v time (crystal oscillator) 60.0 v cc = 2.7 v to 5.5 v 100.0 oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high t cph osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock low t cpl osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock rise time t cpr 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 367 table 14.18 control signal timing of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure external clock fall time t cpf 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 pin res low width t rel res 10 t cyc figure 14.2 input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 368 table 14.19 serial interface (sci1, sci2) timing of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise t sckr sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 input serial clock fall t sckf sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 serial output data t sod so 1 , so 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 delay time 350.0 serial input data t sis si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 setup time 400.0 serial input data t sih si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 hold time 400.0 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 369 table 14.20 serial interface (sci3) timing of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time t txd 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 1 receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 370 14.5.4 a/d converter characteristics table 14.21 shows the a/d converter characteristics of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version). table 14.21 a/d converter characteristics of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 2.5 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 3.0 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v quantization error 0.5 lsb absolute accuracy 2.5 3.5 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v conversion 12.4 124 s av cc = 4.5 v to 5.5 v time 24.8 124 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 371 14.5.5 lcd characteristics table 14.22 lists the lcd characteristics, and table 14.23 lists the ac characteristics for external segment expansion of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version). table 14.22 lcd characteristics of h8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 100.0 300.0 600.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss 372 table 14.23 ac characteristics for external segment expansion of 8/3832s, h8/3833s, and h8/3834s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 373 14.6 h8/3835s, h8/3836s and h8/3837s electrical characteristics (wide temperature range (i-spec) version) 14.6.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3835s, h8/3836s, and h8/3837s are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range of h8/3835s, h8/3836s, and h8/3837s 10.0 2.5 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.5 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speeds) sleep mode ? all operating modes 5.0 2.0 374 2. power supply voltage vs. clock frequency range of h8/3835s, h8/3836s, and h8/3837s 625.0 2.5 4.0 5.5 v (v) cc (khz) 5.0 2.5 4.0 5.5 v (v) cc (mhz) 16.384 2.5 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range of h8/3835s, h8/3836s, and h8/3837s 2.5 4.0 5.5 av (v) cc 2.5 4.0 5.5 av (v) cc 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 (mhz) (khz) f f 375 14.6.2 dc characteristics table 14.24 lists the dc characteristics of the h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version). table 14.24 dc characteristics of h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.8 v cc 0.9 v cc v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 osc 1 v cc C 0.5 v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc C 0.3 v cc + 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.7 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v pb 0 to pb 7 pc 0 to pc 3 0.7 v cc 0.8 v cc av cc + 0.3 av cc + 0.3 vv cc = 4.0 v to 5.5 v input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 C0.3 0.2 v cc 0.1 v cc vv cc = 4.0 v to 5.5 v note: connect pin test to v ss . 376 table 14.24 dc characteristics of h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il ud, si 1 , si 2 , rxd C0.3 C0.3 0.3 v cc 0.2 v cc vv cc = 4.0 v to 5.5 v osc 1 C0.3 0.5 v v cc = 4.0 v to 5.5 v C0.3 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 C0.3 0.3 v cc 0.2 v cc vv cc = 4.0 v to 5.5 v output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 0.5 vv cc = 4.0 v to 5.5 v i ol = 1.6 ma i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma note: connect pin test to v ss . 377 table 14.24 dc characteristics of h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note output low voltage v ol p2 0 to p2 7 p3 0 to p3 7 1.5 v v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 0.5 v cc = 4.0 v to 5.5 v i ol = 1.6 ma i ol = 0.4 ma input/output leakage current |i il | res osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 0 to p1 7 p3 0 to p3 7 p5 0 to p5 7 p6 0 to p6 7 50.0 35.0 300.0 a v cc = 5 v, v in = 0 v v cc = 2.7 v, v in = 0 v reference value input capacitance c in all input pins except power supply 15.0 pf f = 1 mhz, v in = 0 v t a = 25c 378 table 14.24 dc characteristics of h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 9.0 13.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 1.7 3.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 4.0 7.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 30.0 65.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 22.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 20.0 45.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 watch mode current dissipation i watch v cc 5.5 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator 1, 2 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 379 table 14.24 dc characteristics of h8/3835s, h8/3836s and h8/3837s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 all output pins 10.0 0.5 v cc = 4.0 v to 5.5 v allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 all output pins 80.0 20.0 v cc = 4.0 v to 5.5 v allowable output high current (per pin) Ci oh all output pins 2.0 0.2 ma v cc = 4.0 v to 5.5 v allowable output high current (total) s Ci oh all output pins 15.0 10.0 ma v cc = 4.0 v to 5.5 v 380 14.6.3 ac characteristics table 14.25 lists the control signal timing, and tables 14.26 and 14.27 list the serial interface timing of the h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version). table 14.25 control signal timing of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 2.0 10.0 5.0 mhz v cc = 4.0 v to 5.5 v osc clock ( f osc ) cycle time t osc osc 1 , osc 2 100.0 200.0 1000.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 figure 14.1 system clock ( f ) cycle time t cyc 2 16 2000.0 t osc ns 1 subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40.0 60.0 100.0 ms v cc = 4.0 v to 5.5 v v cc = 2.7 v to 5.5 v oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high width t cph osc 1 40.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.1 external clock low width t cpl osc 1 40.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.1 external clock rise timet cpr 15.0 20.0 ns v cc = 4.0 v to 5.5 v figure 14.1 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 381 table 14.25 control signal timing of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) (cont) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure external clock fall time t cpf 15.0 20.0 ns v cc = 4.0 v to 5.5 v figure 14.1 pin res low width t rel res 10 tcyc figure 14.2 input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 382 table 14.26 serial interface (sci1, sci2) timing of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise time t sckr sck 1 , sck 2 60.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.5 input serial clock fall time t sckf sck 1 , sck 2 60.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial output data delay time t sod so 1 , so 2 200.0 350.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial input data setup time t sis si 1 , si 2 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial input data hold time t sih si 1 , si 2 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.5 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 383 table 14.27 serial interface (sci3) timing of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time (synchronous mode) t txd 1 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 receive data setup time (synchronous mode) t rxs 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.8 receive data hold time (synchronous mode) t rxh 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.8 384 14.6.4 a/d converter characteristics table 14.28 shows the a/d converter characteristics of the h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version). table 14.28 a/d converter characteristics of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 2.5 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 3.0 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v quantization error 0.5 lsb absolute accuracy 2.5 3.5 lsb v cc = 2.7 v to 5.5 v av cc = 2.7 v to 5.5 v conversion 12.4 124 s av cc = 4.5 v to 5.5 v time 24.8 124 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 385 14.6.5 lcd characteristics table 14.29 lists the lcd characteristics, and table 14.30 lists the ac characteristics for external segment expansion of the h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version). table 14.29 lcd characteristics of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 100.0 300.0 600.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss 386 table 14.30 ac characteristics for external segment expansion of h8/3835s, h8/3836s, and h8/3837s (wide temperature range (i-spec) version) v cc = 2.5 v to 5.5 v, av cc = 2.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 387 14.7 h8/3833, h8/3834, h8/3835, h8/3836, and h8/3837 (standard specification) absolute maximum ratings table 14.31 lists the absolute maximum ratings. table 14.31 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +7.0 v analog power supply voltage av cc C0.3 to +7.0 v programming voltage v pp C0.3 to + 13.0 v input voltage ports other than ports b and c v in C0.3 to v cc + 3.0 v ports b and c av in C0.3 to av cc + 3.0 v operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 388 14.8 h8/3833 and h8/3834 electrical characteristics (standard specifications) 14.8.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3833 and h8/3834 are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range of h8/3833 and h8/3834 10.0 2.7 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.7 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speed) sleep mode ? all operating modes 5.0 2.0 389 2. power supply voltage vs. clock frequency range of h8/3833 and h8/3834 625.0 2.7 4.0 5.5 v (v) cc (khz) 5.0 2.7 4.0 5.5 v (v) cc (mhz) 16.384 2.7 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range of h8/3833 and h8/3834 2.7 4.0 5.5 av (v) cc (mhz) 2.7 4.0 5.5 av (v) cc (khz) 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 f f 390 14.8.2 dc characteristics table 14.32 lists the dc characteristics of the h8/3833 and h8/3834. table 14.32 dc characteristics of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.8 v cc 0.9 v cc v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v ud, si 1 , si 2 , rxd 0.7 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v osc 1 v cc C 0.5 v cc C 0.3 v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.7 v cc 0.8 v cc v cc + 0.3 v cc + 0.3 vv cc = 4.0 v to 5.5 v pb 0 to pb 7 pc 0 to pc 3 0.7 v cc 0.8 v cc av cc + 0.3 av cc + 0.3 vv cc = 4.0 v to 5.5 v input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 C0.3 0.2 v cc 0.1 v cc vv cc = 4.0 v to 5.5 v ud, si 1 , si 2 , rxd C0.3 C0.3 0.3 v cc 0.2 v cc vv cc = 4.0 v to 5.5 v osc 1 C0.3 C0.3 0.5 0.3 vv cc = 4.0 v to 5.5 v note: connect pin test to v ss . 391 table 14.32 dc characteristics of h8/3833 and h8/3834 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 C0.3 0.3 v cc 0.2 v cc vv cc = 4.0 v to 5.5 v output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 0.5 vv cc = 4.0 v to 5.5 v i ol = 1.6 ma i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 0.5 v cc = 4.0 v to 5.5 v i ol = 1.6 ma i ol = 0.4 ma note: connect pin test to v ss . 392 table 14.32 dc characteristics of h8/3833 and h8/3834 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input/output leakage |i il | res , p4 3 20.0 a v in = 0.5 v to v cc C 0.5 v 2 current 1.0 1 osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 0 to p1 7 p3 0 to p3 7 p5 0 to p5 7 p6 0 to p6 7 50.0 35.0 300.0 a v cc = 5 v, v in = 0 v v cc = 2.7 v, v in = 0 v reference value input capacitance c in all input pins except power supply, res , p4 3 pin 15.0 pf f = 1 mhz, v in = 0 v t a = 25c res 60.0 2 15.0 1 p4 3 30.0 2 15.0 1 notes: 1. applies to hd6433833 and hd6433834. 2. applies to hd6473834. 393 table 14.32 dc characteristics of h8/3833 and h8/3834 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 12.0 24.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 3, 4 dissipation i ope2 v cc 2.5 5.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 3, 4 sleep mode current dissipation i sleep v cc 5.0 10.0 ma v cc = 5 v, f osc = 10 mhz 3, 4 subactive mode current dissipation i sub v cc 50.0 130.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) reference value 3, 4 40.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 3, 4 subsleep mode current dissipation i subsp v cc 40.0 90.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) reference value 3, 4 watch mode current dissipation i watch v cc 6.0 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator reference value 3, 4 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 3, 4 ram data retaining voltage v ram v cc 2.0 v 3, 4 notes: 3. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 4. excludes current in pull-up mos transistors and output buffers. 394 table 14.32 dc characteristics of h8/3833 and h8/3834 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 10.0 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 80.0 v cc = 4.0 v to 5.5 v all output pins 20.0 allowable output high current (per pin) Ci oh all output pins 2.0 0.2 ma v cc = 4.0 v to 5.5 v allowable output high current (total) s Ci oh all output pins 15.0 10.0 ma v cc = 4.0 v to 5.5 v 395 14.8.3 ac characteristics table 14.33 lists the control signal timing, and tables 14.34 and 14.35 list the serial interface timing of the h8/3833 and h8/3834. table 14.33 control signal timing of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 2.0 10.0 5.0 mhz v cc = 4.0 v to 5.5 v osc clock ( f osc ) cycle time t osc osc 1 , osc 2 100.0 200.0 1000.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40.0 60.0 ms v cc = 4.0 v to 5.5 v oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high width t cph osc 1 40.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.1 external clock low width t cpl osc 1 40.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.1 external clock rise time t cpr 15.0 20.0 ns v cc = 4.0 v to 5.5 v figure 14.1 external clock fall time t cpf 15.0 20.0 ns v cc = 4.0 v to 5.5 v figure 14.1 pin res low width t rel res 10 tcyc figure 14.2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 396 table 14.33 control signal timing of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 397 table 14.34 serial interface (sci1, sci2) timing of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise time t sckr sck 1 , sck 2 60.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.5 input serial clock fall time t sckf sck 1 , sck 2 60.0 80.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial output data delay time t sod so 1 , so 2 200.0 350.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial input data setup time t sis si 1 , si 2 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.5 serial input data hold time t sih si 1 , si 2 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.5 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 398 table 14.35 serial interface (sci3) timing of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time (synchronous mode) t txd 1 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 receive data setup time (synchronous mode) t rxs 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.8 receive data hold time (synchronous mode) t rxh 200.0 400.0 ns v cc = 4.0 v to 5.5 v figure 14.8 399 14.8.4 a/d converter characteristics table 14.36 shows the a/d converter characteristics of the h8/3833 and h8/3834. table 14.36 a/d converter characteristics of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 4.0 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb conversion time 12.4 24.8 124 124 s av cc = 4.5 v to 5.5 v notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 400 14.8.5 lcd characteristics table 14.37 lists the lcd characteristics, and table 14.38 lists the ac characteristics for external segment expansion of the h8/3833 and h8/3834. table 14.37 lcd characteristics of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 50.0 300.0 900.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss table 14.38 ac characteristics for external segment expansion of h8/3833 and h8/3834 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 401 14.9 h8/3835 and h8/3836 and h8/3837 (standard specifications) electrical characteristics 14.9.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3835, h8/3836 and h8/3837 are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range of h8/3835, h8/3836 and h8/3837 10.0 2.7 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.7 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speed) sleep mode ? all operating modes 5.0 2.0 402 2. power supply voltage vs. clock frequency range of h8/3835, h8/3836 and h8/3837 625.0 2.7 4.0 5.5 v (v) cc (khz) 5.0 2.7 4.0 5.5 v (v) cc (mhz) 16.384 2.7 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 f f f 3. analog power supply voltage vs. a/d converter operating range of h8/3835, h8/3836 and h8/3837 2.7 4.0 5.5 av (v) cc (mhz) 2.7 4.0 5.5 av (v) cc (khz) 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 f f 403 14.9.2 dc characteristics table 14.39 lists the dc characteristics of the h8/3835, h8/3836 and h8/3837. table 14.39 dc characteristics of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.9 v cc v cc + 0.3 ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 osc 1 v cc C 0.5 v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc C 0.3 v cc + 0.3 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.8 v cc v cc + 0.3 pb 0 to pb 7 0.7 v cc av cc + 0.3 v v cc = 4.0 v to 5.5 v pc 0 to pc 3 0.8 v cc av cc + 0.3 input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.1 v cc ud, si 1 , si 2 , rxd C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v C0.3 0.2 v cc osc 1 C0.3 0.5 v v cc = 4.0 v to 5.5 v C0.3 0.3 note: connect pin test to v ss . 404 table 14.39 dc characteristics of h8/3835, h8/3836 and h8/3837 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.2 v cc output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.1 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma note: connect pin test to v ss . 405 table 14.39 dc characteristics of h8/3835, h8/3836 and h8/3837 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input/output leakage |i il | res , p4 3 20.0 a v in = 0.5 v to v cc C 0.5 v 2 current 1.0 1 osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 1.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 1.0 v in = 0.5 v to av cc C 0.5 v pull-up mos Ci p p1 0 to p1 7 p3 0 to p3 7 50.0 330.0 a v cc = 5 v, v in = 0 v current p5 0 to p5 7 p6 0 to p6 7 35.0 a v cc = 2.7 v, v in = 0 v reference value input capacitance c in all input pins except power supply, res , p4 3 pin 15.0 pf f = 1 mhz, v in = 0 v t a = 25c res 60.0 2 15.0 1 p4 3 30.0 2 15.0 1 notes: 1. applies to hd6433835, hd6433836 and hd6433837. 2. applies to hd6473837. 406 table 14.39 dc characteristics of h8/3835, h8/3836 and h8/3837 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 13.5 24.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 3, 4 dissipation i ope2 v cc 2.5 5.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 3, 4 sleep mode current dissipation i sleep v cc 5.0 10.0 ma v cc = 5 v, f osc = 10 mhz 3, 4 subactive mode current dissipation i sub v cc 50.0 130.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) reference value 3, 4 40.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 3, 4 subsleep mode current dissipation i subsp v cc 40.0 a v cc = 2.7 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) reference value 3, 4 watch mode current dissipation i watch v cc 6.0 a v cc = 2.7 v, lcd not used, 32-khz crystal oscillator reference value 3, 4 standby mode current dissipation i stby v cc 5.0 a 32-khz crystal oscillator not used 3, 4 ram data retaining voltage v ram v cc 2.0 v 3, 4 notes: 3. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 4. excludes current in pull-up mos transistors and output buffers. 407 table 14.39 dc characteristics of h8/3835, h8/3836 and h8/3837 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 10.0 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma v cc = 4.0 v to 5.5 v ports 2 and 3 80.0 v cc = 4.0 v to 5.5 v all output pins 20.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v 0.2 allowable output high current (total) s Ci oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v 10.0 408 14.9.3 ac characteristics table 14.40 lists the control signal timing, and tables 14.41 and 14.42 list the serial interface timing of the h8/3835, h8/3836 and h8/3837. table 14.40 control signal timing of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock f osc osc 1 , osc 2 2.0 10.0 mhz v cc = 4.0 v to 5.5 v oscillation frequency 2.0 5.0 osc clock ( f osc )t osc osc 1 , osc 2 100.0 1000.0 ns v cc = 4.0 v to 5.5 v 1 cycle time 200.0 1000.0 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization t rc osc 1 , osc 2 40.0 ms v cc = 4.0 v to 5.5 v time (crystal oscillator) 60.0 oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high t cph osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock low t cpl osc 1 40.0 ns v cc = 4.0 v to 5.5 v figure 14.1 width 80.0 external clock rise time t cpr 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 external clock fall time t cpf 15.0 ns v cc = 4.0 v to 5.5 v figure 14.1 20.0 pin res low width t rel res 10 t cyc figure 14.2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 409 table 14.40 control signal timing of h8/3835, h8/3836 and h8/3837 (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 410 table 14.41 serial interface (sci1, sci2) timing of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise t sckr sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 input serial clock fall t sckf sck 1 , sck 2 60.0 ns v cc = 4.0 v to 5.5 v figure 14.5 time 80.0 serial output data t sod so 1 , so 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 delay time 350.0 serial input data t sis si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 setup time 400.0 serial input data t sih si 1 , si 2 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 hold time 400.0 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 411 table 14.42 serial interface (sci3) timing of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time t txd 1 t cyc v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 1 receive data setup time t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 receive data hold time t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.8 (synchronous mode) 400.0 412 14.9.4 a/d converter characteristics table 14.43 shows the a/d converter characteristics of the h8/3835, h8/3836 and h8/3837. table 14.43 a/d converter characteristics of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, t a = C20c to +75c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 4.0 5.5 v 1 analog input voltage av in an 0 to an 11 av ss C 0.3 av cc + 0.3 v analog power ai ope av cc 1.5 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 5.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb conversion 12.4 124 s v cc = 4.0 v to 5.5 v time 24.8 124 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 413 14.9.5 lcd characteristics table 14.44 lists the lcd characteristics, and table 14.45 lists the ac characteristics for external segment expansion of the h8/3835, h8/3836 and h8/3837. table 14.44 lcd characteristics of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 50.0 300.0 900.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 2.7 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss table 14.45 ac characteristics for external segment expansion of h8/3835, h8/3836 and h8/3837 v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 414 14.10 h8/3833, h8/3834, h8/3835, h8/3836, and h8/3837 absolute maximum ratings (wide temperature range (i-spec) version) table 14.46 lists the absolute maximum ratings. table 14.46 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +7.0 v analog power supply voltage av cc C0.3 to +7.0 v programming voltage v pp C0.3 to + 13.0 v input voltage ports other than ports b and c v in C0.3 to v cc + 3.0 v ports b and c av in C0.3 to av cc + 3.0 v operating temperature t opr C20 to +75 c storage temperature t stg C55 to +125 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 415 14.11 h8/3833 and h8/3834 electrical characteristics (wide temperature range (i-spec) version) 14.11.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3833 and h8/3834 (wide temperature range (i-spec) version) are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range 10.0 2.7 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.7 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speed) sleep mode ? all operating modes 5.0 2.0 4.5 4.5 416 2. power supply voltage vs. clock frequency range 625.0 2.7 4.0 5.5 v (v) cc (khz) 5.0 2.7 4.0 5.5 v (v) cc (mhz) 16.384 2.7 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 4.5 4.5 4.5 f f f 3. analog power supply voltage vs. a/d converter operating range 2.7 4.0 5.5 av (v) cc 2.7 4.0 5.5 av (v) cc 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 4.5 4.5 (mhz) (khz) f f 417 14.11.2 dc characteristics table 14.47 lists the dc characteristics of the h8/3833 and h8/3834 (wide temperature range (i- spec) version). table 14.47 dc characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.8 v cc v cc + 0.3 v ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v osc 1 v cc C 0.5 v cc + 0.3 v p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.7 v cc v cc + 0.3 v pb 0 to pb 7 pc 0 to pc 3 0.7 v cc av cc + 0.3 v input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.2 v cc v ud, si 1 , si 2 , rxd C0.3 0.3 v cc v osc 1 C0.3 0.5 v note: connect pin test to v ss . 418 table 14.47 dc characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.3 v cc v output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.5 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v i ol = 1.6 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 1.5 i ol = 10 ma p3 0 to p3 7 0.6 i ol = 1.6 ma note: connect pin test to v ss . 419 table 14.47 dc characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input/output leakage |i il | res , p4 3 24.0 a v in = 0.5 v to v cc C 0.5 v 2 current 2.0 1 osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 2.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 2.0 v in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 0 to p1 7 p3 0 to p3 7 p5 0 to p5 7 p6 0 to p6 7 20.0 330.0 a v cc = 5 v, v in = 0 v input capacitance c in all input pins except power supply, res , p4 3 pin 15.0 pf f = 1 mhz, v in = 0 v t a = 25c res 60.0 2 15.0 1 p4 3 30.0 2 15.0 1 notes: 1. applies to hd6433833 and hd6433834 (wide temperature range version). 2. applies to hd6473834 (wide temperature range version). 420 table 14.47 dc characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 12.0 30.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 2.5 6.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 5.0 12.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 100.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 reference value 70.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 60.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 reference value watch mode current dissipation i watch v cc 6.0 a v cc = 5 v, lcd not used, 32-khz crystal oscillator 1, 2 reference value standby mode current dissipation i stby v cc 10.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 421 table 14.47 dc characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma ports 2 and 3 10.0 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma ports 2 and 3 80.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma allowable output high current (total) s Ci oh all output pins 15.0 ma 422 14.11.3 ac characteristics table 14.48 lists the control signal timing, and tables 14.49 and 14.50 list the serial interface timing of the h8/3833 and h8/3834 (wide temperature range (i-spec) version). table 14.48 control signal timing of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to + 85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 10.0 mhz osc clock ( f osc ) cycle time t osc osc 1 , osc 2 100.0 1000.0 ns 1 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40.0 ms oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high width t cph osc 1 40.0 ns figure 14.1 external clock low width t cpl osc 1 40.0 ns figure 14.1 external clock rise time t cpr 15.0 ns figure 14.1 external clock fall time t cpf 15.0 ns figure 14.1 pin res low width t rel res 10 tcyc figure 14.2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 423 table 14.48 control signal timing of h8/3833 and h8/3834 (wide temperature range (i-spec) version) (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 424 table 14.49 serial interface (sci1, sci2) timing of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise time t sckr sck 1 , sck 2 60.0 ns figure 14.5 input serial clock fall time t sckf sck 1 , sck 2 60.0 ns figure 14.5 serial output data delay time t sod so 1 , so 2 200.0 ns figure 14.5 serial input data setup time t sis si 1 , si 2 200.0 ns figure 14.5 serial input data hold time t sih si 1 , si 2 200.0 ns figure 14.5 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 425 table 14.50 serial interface (sci3) timing of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time (synchronous mode) t txd 1 t cyc figure 14.8 receive data setup time (synchronous mode) t rxs 200.0 ns figure 14.8 receive data hold time (synchronous mode) t rxh 200.0 ns figure 14.8 426 14.11.4 a/d converter characteristics table 14.51 shows the a/d converter characteristics of the h8/3833s and h8/3834s (wide temperature range (i-spec) version). table 14.51 a/d converter characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 4.5 5.5 v 1 analog input voltage av in an 0 to an 11 C0.3 av cc + 0.3 v analog power ai ope av cc 1.7 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 7.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb conversion time 12.4 124 s notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 427 14.11.5 lcd characteristics table 14.52 lists the lcd characteristics, and table 14.53 lists the ac characteristics for external segment expansion of the h8/3833 and h8/3834 (wide temperature range (i-spec) version). table 14.52 lcd characteristics of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 40.0 300.0 1000.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 4.5 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss 428 table 14.53 ac characteristics for external segment expansion of h8/3833 and h8/3834 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 429 14.12 h8/3835, h8/3836, and h8/3837 electrical characteristics (wide temperature range (i-spec) version) 14.12.1 power supply voltage and operating range the power supply voltage and operating range of the h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range 10.0 2.7 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.7 4.0 5.5 v (v) cc fw (khz) ? ? active mode (high speeds) sleep mode ? all operating modes 5.0 2.0 4.5 4.5 430 2. power supply voltage vs. clock frequency range 625.0 2.7 4.0 5.5 v (v) cc (khz) 5.0 2.7 4.0 5.5 v (v) cc (mhz) 16.384 2.7 4.0 5.5 v (v) cc (khz) sub ? ? active mode (high speed) sleep mode (except cpu) ? ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 4.5 4.5 4.5 f f f 3. analog power supply voltage vs. a/d converter operating range 2.7 4.0 5.5 av (v) cc 2.7 4.0 5.5 av (v) cc 625.0 312.5 ? ? active (high speed) mode sleep mode ? active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 4.5 4.5 (mhz) (khz) f f 431 14.12.2 dc characteristics table 14.54 lists the dc characteristics of the h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version). table 14.54 dc characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif cs , tmig, sck 1 , sck 2 , sck 3 , adtrg 0.8 v cc v cc + 0.3 v ud, si 1 , si 2 , rxd 0.7 v cc v cc + 0.3 v osc 1 v cc C 0.5 v cc + 0.3 v p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.7 v cc v cc + 0.3 v pb 0 to pb 7 pc 0 to pc 3 0.7 v cc av cc + 0.3 v input low voltage v il res , md0, wkp 0 to wkp 7 , irq 0 to irq 4 , tmib, tmic, tmif, cs , tmig, sck 1 , sck 2 , sck 3 , adtrg C0.3 0.2 v cc v ud, si 1 , si 2 , rxd C0.3 0.3 v cc v osc 1 C0.3 0.5 v note: connect pin test to v ss . 432 table 14.54 dc characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 3 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 pb 0 to pb 7 pc 0 to pc 3 C0.3 0.3 v cc v output high voltage v oh p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 v cc C 1.0 v Ci oh = 1.0 ma p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 v cc C 0.5 Ci oh = 0.5 ma output low voltage v ol p1 0 to p1 7 p4 0 to p4 2 0.6 v i ol = 1.6 ma p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 0.5 i ol = 0.4 ma p2 0 to p2 7 1.5 i ol = 10 ma p3 0 to p3 7 0.6 i ol = 1.6 ma note: connect pin test to v ss . 433 table 14.54 dc characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input/output leakage |i il | res , p4 3 24.0 a v in = 0.5 v to v cc C 0.5 v 2 current 2.0 1 osc 1 , md0 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 2 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p9 0 to p9 7 pa 0 to pa 3 2.0 a v in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 pc 0 to pc 3 2.0 v in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 0 to p1 7 p3 0 to p3 7 p5 0 to p5 7 p6 0 to p6 7 20.0 330.0 a v cc = 5 v, v in = 0 v input capacitance c in all input pins except power supply, res , p4 3 pin 15.0 pf f = 1 mhz, v in = 0 v t a = 25c res 60.0 2 15.0 1 p4 3 30.0 2 15.0 1 notes: 1. applies to hd6433835, hd6433836, and hd6433837 (wide temperature range version). 2. applies to hd6473837 (wide temperature range version). 434 table 14.54 dc characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note active mode current i ope1 v cc 13.5 30.0 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 1, 2 dissipation i ope2 v cc 2.5 6.0 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 1, 2 sleep mode current dissipation i sleep v cc 5.0 12.0 ma v cc = 5 v, f osc = 10 mhz 1, 2 subactive mode current dissipation i sub v cc 100.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 reference value 70.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/8) reference value 1, 2 subsleep mode current dissipation i subsp v cc 60.0 a v cc = 5 v, lcd on, 32-khz crystal oscillator ( f sub = f w/2) 1, 2 reference value watch mode current dissipation i watch v cc 6.0 a v cc = 5 v, lcd not used, 32-khz crystal oscillator 1, 2 reference value standby mode current dissipation i stby v cc 10.0 a 32-khz crystal oscillator not used 1, 2 ram data retaining voltage v ram v cc 2.0 v 1, 2 notes: 1. pin states during current measurement mode internal state other pins lcd power supply oscillator pins active mode (high and medium speed) operates v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode only timer operates v cc open subactive mode operates v cc open system clock oscillator: crystal subsleep mode only timer operates, cpu stops v cc open subclock oscillator: crystal watch mode only time-base clock operates, cpu stops v cc open standby mode cpu and timers all stop v cc open system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 2. excludes current in pull-up mos transistors and output buffers. 435 table 14.54 dc characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) (cont) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 2 and 3 2.0 ma ports 2 and 3 10.0 allowable output low current (total) s i ol output pins except in ports 2 and 3 40.0 ma ports 2 and 3 80.0 allowable output high current (per pin) Ci oh all output pins 2.0 ma allowable output high current (total) s Ci oh all output pins 15.0 ma 436 14.12.3 ac characteristics table 14.55 lists the control signal timing, and tables 14.56 and 14.57 list the serial interface timing of the h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version). table 14.55 control signal timing of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 10.0 mhz osc clock ( f osc ) cycle time t osc osc 1 , osc 2 100.0 1000.0 ns 1 figure 14.1 system clock ( f )t cyc 2 16 t osc 1 cycle time 2000.0 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock ( f w ) cycle time t w x 1 , x 2 30.5 s subclock ( f sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40.0 ms oscillation stabilization time t rc x 1 , x 2 2.0 s external clock high width t cph osc 1 40.0 ns figure 14.1 external clock low width t cpl osc 1 40.0 ns figure 14.1 external clock rise time t cpr 15.0 ns figure 14.1 external clock fall time t cpf 15.0 ns figure 14.1 pin res low width t rel res 10 tcyc figure 14.2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system control register 2 (syscr2). 437 table 14.55 control signal timing of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) (cont) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 wkp 0 to wkp 7 adtrg tmib, tmic tmif, tmig 2 t cyc t subcyc figure 14.3 pin ud minimum modulation width t udh t udl ud 4 t cyc t subcyc figure 14.4 438 table 14.56 serial interface (sci1, sci2) timing of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 , sck 2 2 t cyc figure 14.5 input serial clock high width t sckh sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock low width t sckl sck 1 , sck 2 0.4 t scyc figure 14.5 input serial clock rise time t sckr sck 1 , sck 2 60.0 ns figure 14.5 input serial clock fall time t sckf sck 1 , sck 2 60.0 ns figure 14.5 serial output data delay time t sod so 1 , so 2 200.0 ns figure 14.5 serial input data setup time t sis si 1 , si 2 200.0 ns figure 14.5 serial input data hold time t sih si 1 , si 2 200.0 ns figure 14.5 cs setup time t css cs 2 t cyc figure 14.6 cs hold time t csh cs 2 t cyc figure 14.6 439 table 14.57 serial interface (sci3) timing of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.7 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.7 transmit data delay time (synchronous mode) t txd 1 t cyc figure 14.8 receive data setup time (synchronous mode) t rxs 200.0 ns figure 14.8 receive data hold time (synchronous mode) t rxh 200.0 ns figure 14.8 440 14.12.4 a/d converter characteristics table 14.58 shows the a/d converter characteristics of the h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version). table 14.58 a/d converter characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40c to +85c, unless otherwise specified. item symbol applicable pins min typ max unit test condition note analog power supply voltage av cc av cc 4.5 5.5 v 1 analog input voltage av in an 0 to an 11 av ss C0.3 av cc + 0.3 v analog power ai ope av cc 1.7 ma av cc = 5.0 v supply current ai stop1 av cc 150.0 a 2 reference value ai stop2 av cc 7.0 a 3 analog input capacitance c ain an 0 to an 11 30.0 pf allowable signal source impedance r ain 10.0 k w resolution (data length) 8 bit non-linearity error 2.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb conversion time 12.4 124 s notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 441 14.12.5 lcd characteristics table 14.59 lists the lcd characteristics, and table 14.60 lists the ac characteristics for external segment expansion of the h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version). table 14.59 lcd characteristics of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition note segment driver voltage drop v ds seg 1 to seg 40 0.6 v i d = 2 a 1 common driver voltage drop v dc com 1 to com 4 0.3 v i d = 2 a 1 lcd power supply voltage divider resistance r lcd 40.0 300.0 100.0 k w between v 1 and v ss lcd power supply voltage v lcd v 1 4.5 v cc v2 notes: 1. these are the voltage drops between the voltage supply pins v 1 , v 2 , v 3 , and v ss , and the segment pins or common pins. 2. when v lcd is supplied from an external source, the following relation must hold: v cc 3 v 1 3 v 2 3 v 3 3 v ss 442 table 14.60 ac characteristics for external segment expansion of h8/3835, h8/3836, and h8/3837 (wide temperature range (i-spec) version) v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = C40c to +85c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure clock high width t cwh cl 1, cl 2 800.0 ns * figure 14.9 clock low width t cwl cl 2 800.0 ns * figure 14.9 clock setup time t csu cl 1, cl 2 500.0 ns * figure 14.9 data setup time t su do 300.0 ns * figure 14.9 data hold time t dh do 300.0 ns * figure 14.9 m delay time t dm m C1000 1000.0 ns figure 14.9 clock rise and fall times t ct cl 1, cl 2 100.0 ns figure 14.9 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. 443 14.13 operation timing figures 14.1 to 14.9 show timing diagrams. t osc v ih v il t cph t cpl t cpr osc t cpf 1 figure 14.1 system clock input timing res v il t rel figure 14.2 res low width timing v ih v il t il irq to irq wkp to wkp adtrg tmib, tmic tmif, tmig t ih 04 07 figure 14.3 input timing 444 ud v ih v il t udl t udh figure 14.4 ud pin minimum transition width timing 445 t scyc t sckf t sckl t sckh t sod v v oh ol * * t sis t sih sck sck so so si si 1 2 1 2 1 2 t sckr v or v ih oh * v or v il ol * notes: * output timing reference levels output high: output low: load conditions are shown in figure 14-10. v = 1.8 v (v cc = 2.5 v to 5.5 v)/2.0 v (v cc = 2.7 v to 5.5 v) v = 0.8 v oh ol figure 14.5 serial interface 1 and 2 input/output timing 446 t css t csh v ih v il cs sck 2 v ih v il figure 14.6 serial interface 2 chip select timing sck 3 t sckw t scyc figure 14.7 sck 3 input clock timing 447 sck txd (receive data) txd (transmit data) 3 t scyc t txd t rxh t rxs v v oh ol * * v or v ih oh * v or v il ol * notes: * output timing reference levels output high: output low: load conditions are shown in figure 14-10. v = 1.8 v (v cc = 2.5 v to 5.5 v)/2.0 v (v cc = 2.7 v to 5.5 v) v = 0.8 v oh ol figure 14.8 input/output timing of serial interface 3 in synchronous mode cl cl do m 1 2 t ct t cwh t cwh t csu t csu t ct t cwl t su t dh t dm v C 0.5 v cc 0.4 v cc v C 0.5 v cc v C 0.5 v 0.4 v 0.4 v 0.4 v figure 14.9 segment expansion signal timing 448 14.14 output load circuit v cc 2.4 k w 12 k w 30 pf output pin figure 14.10 output load condition 449 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition C subtraction multiplication division logical and logical or ? exclusive logical or ? move logical complement condition code notation symbol modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result 450 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states mov.b #xx:8, rd b #xx:8 ? rd8 2 02 mov.b rs, rd b rs8 ? rd8 2 02 mov.b @rs, rd b @rs16 ? rd8 2 04 mov.b @(d:16, rs), rd b @(d:16, rs16) ? rd8 4 06 mov.b @rs+, rd b @rs16 ? rd8 rs16+1 ? rs16 2 06 mov.b @aa:8, rd b @aa:8 ? rd8 2 04 mov.b @aa:16, rd b @aa:16 ? rd8 4 06 mov.b rs, @rd b rs8 ? @rd16 2 04 mov.b rs, @(d:16, rd) b rs8 ? @(d:16, rd16) 4 06 mov.b rs, @Crd b rd16C1 ? rd16 rs8 ? @rd16 2 06 mov.b rs, @aa:8 b rs8 ? @aa:8 2 04 mov.b rs, @aa:16 b rs8 ? @aa:16 4 06 mov.w #xx:16, rd w #xx:16 ? rd 4 04 mov.w rs, rd w rs16 ? rd16 2 02 mov.w @rs, rd w @rs16 ? rd16 2 04 mov.w @(d:16, rs), rd w @(d:16, rs16) ? rd16 4 06 mov.w @rs+, rd w @rs16 ? rd16 rs16+2 ? rs16 2 06 mov.w @aa:16, rd w @aa:16 ? rd16 4 06 mov.w rs, @rd w rs16 ? @rd16 2 04 mov.w rs, @(d:16, rd) w rs16 ? @(d:16, rd16) 4 06 mov.w rs, @Crd w rd16C2 ? rd16 rs16 ? @rd16 2 06 mov.w rs, @aa:16 w rs16 ? @aa:16 4 06 pop rd w @sp ? rd16 sp+2 ? sp 2 06 451 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states push rs w spC2 ? sp rs16 ? @sp 2 06 eepmov if r4l 1 0 then repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4lC1 ? r4l until r4l=0 else next; 4 (4) add.b #xx:8, rd b rd8+#xx:8 ? rd8 2 2 add.b rs, rd b rd8+rs8 ? rd8 2 2 add.w rs, rd w rd16+rs16 ? rd16 2 (1) 2 addx.b #xx:8, rd b rd8+#xx:8 +c ? rd8 2 (2) 2 addx.b rs, rd b rd8+rs8 +c ? rd8 2 (2) 2 adds.w #1, rd w rd16+1 ? rd16 2 2 adds.w #2, rd w rd16+2 ? rd16 2 2 inc.b rd b rd8+1 ? rd8 2 2 daa.b rd b rd8 decimal adjust ? rd8 2 * * (3) 2 sub.b rs, rd b rd8Crs8 ? rd8 2 2 sub.w rs, rd w rd16Crs16 ? rd16 2 (1) 2 subx.b #xx:8, rd b rd8C#xx:8 Cc ? rd8 2 (2) 2 subx.b rs, rd b rd8Crs8 Cc ? rd8 2 (2) 2 subs.w #1, rd w rd16C1 ? rd16 2 2 subs.w #2, rd w rd16C2 ? rd16 2 2 dec.b rd b rd8C1 ? rd8 2 2 das.b rd b rd8 decimal adjust ? rd8 2 * * 2 neg.b rd b 0Crd ? rd 2 2 cmp.b #xx:8, rd b rd8C#xx:8 2 2 cmp.b rs, rd b rd8Crs8 2 2 cmp.w rs, rd w rd16Crs16 2 (1) 2 mulxu.b rs, rd b rd8 rs8 ? rd16 2 14 452 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states divxu.b rs, rd b rd16 ? rs8 ? rd16 (rdh: remainder, rdl: quotient) 2 (5) (6) 14 and.b #xx:8, rd b rd8 #xx:8 ? rd8 2 02 and.b rs, rd b rd8 rs8 ? rd8 2 02 or.b #xx:8, rd b rd8 #xx:8 ? rd8 2 02 or.b rs, rd b rd8 rs8 ? rd8 2 02 xor.b #xx:8, rd b rd8 ? #xx:8 ? rd8 2 02 xor.b rs, rd b rd8 ? rs8 ? rd8 2 02 not.b rd b rd ? rd 2 02 shal.b rd b b 7 b 0 0 c 2 2 shar.b rd b c b 7 b 0 2 0 2 shll.b rd b b 7 b 0 0 c 2 0 2 shlr.b rd b b 7 b 0 0c 20 0 2 rotxl.b rd b c b 7 b 0 2 0 2 rotxr.b rd b c b 7 b 0 2 0 2 rotl.b rd b c b 7 b 0 2 0 2 rotr.b rd b c b 7 b 0 2 0 2 453 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states bset #xx:3, rd b (#xx:3 of rd8) ? 1 2 2 bset #xx:3, @rd b (#xx:3 of @rd16) ? 1 4 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 1 4 8 bset rn, rd b (rn8 of rd8) ? 1 2 2 bset rn, @rd b (rn8 of @rd16) ? 1 4 8 bset rn, @aa:8 b (rn8 of @aa:8) ? 1 4 8 bclr #xx:3, rd b (#xx:3 of rd8) ? 0 2 2 bclr #xx:3, @rd b (#xx:3 of @rd16) ? 0 4 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 0 4 8 bclr rn, rd b (rn8 of rd8) ? 0 2 2 bclr rn, @rd b (rn8 of @rd16) ? 0 4 8 bclr rn, @aa:8 b (rn8 of @aa:8) ? 0 4 8 bnot #xx:3, rd b (#xx:3 of rd8) ? ( #xx:3 of rd8 ) 2 2 bnot #xx:3, @rd b (#xx:3 of @rd16) ? ( #xx:3 of @rd16 ) 4 8 bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) ? ( #xx:3 of @aa:8 ) 4 8 bnot rn, rd b (rn8 of rd8) ? ( rn8 of rd8 ) 2 2 bnot rn, @rd b (rn8 of @rd16) ? ( rn8 of @rd16 ) 4 8 bnot rn, @aa:8 b (rn8 of @aa:8) ? ( rn8 of @aa:8 ) 4 8 btst #xx:3, rd b ( #xx:3 of rd8 ) ? z 2 2 btst #xx:3, @rd b ( #xx:3 of @rd16 ) ? z 4 6 btst #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) ? z 4 6 btst rn, rd b ( rn8 of rd8 ) ? z 2 2 btst rn, @rd b ( rn8 of @rd16 ) ? z 4 6 btst rn, @aa:8 b ( rn8 of @aa:8 ) ? z 4 6 454 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states bld #xx:3, rd b (#xx:3 of rd8) ? c 2 2 bld #xx:3, @rd b (#xx:3 of @rd16) ? c 4 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 6 bild #xx:3, rd b ( #xx:3 of rd8 ) ? c 2 2 bild #xx:3, @rd b ( #xx:3 of @rd16 ) ? c 4 6 bild #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) ? c 4 6 bst #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bst #xx:3, @rd b c ? (#xx:3 of @rd16) 4 8 bst #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bist #xx:3, @rd b c ? (#xx:3 of @rd16) 4 8 bist #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 band #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 biand #xx:3, rd b c ( #xx:3 of rd8 ) ? c 2 2 biand #xx:3, @rd b c ( #xx:3 of @rd16 ) ? c 4 6 biand #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) ? c 4 6 bor #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 bor #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bior #xx:3, rd b c ( #xx:3 of rd8 ) ? c 2 2 bior #xx:3, @rd b c ( #xx:3 of @rd16 ) ? c 4 6 bior #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) ? c 4 6 bxor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 2 bxor #xx:3, @rd b c ? (#xx:3 of @rd16) ? c 4 6 bxor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 6 bixor #xx:3, rd b c ? ( #xx:3 of rd8 ) ? c 2 2 455 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation branching condition #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states bixor #xx:3, @rd b c ? ( #xx:3 of @rd16 ) ? c 4 6 bixor #xx:3, @aa:8 b c ? ( #xx:3 of @aa:8 ) ? c 4 6 bra d:8 (bt d:8) pc ? pc+d:8 2 4 brn d:8 (bf d:8) pc ? pc+2 2 4 bhi d:8 if c z = 0 2 4 bls d:8 condition c z = 1 2 4 bcc d:8 (bhs d:8) is true c = 0 2 4 bcs d:8 (blo d:8) then c = 1 2 4 bne d:8 pc ? z = 0 2 4 beq d:8 pc+d:8 z = 1 2 4 bvc d:8 else next; v = 0 2 4 bvs d:8 v = 1 2 4 bpl d:8 n = 0 2 4 bmi d:8 n = 1 2 4 bge d:8 n ? v = 0 2 4 blt d:8 n ? v = 1 2 4 bgt d:8 z (n ? v) = 0 2 4 ble d:8 z (n ? v) = 1 2 4 jmp @rn pc ? rn16 2 4 jmp @aa:16 pc ? aa:16 4 6 jmp @@aa:8 pc ? @aa:8 2 8 bsr d:8 spC2 ? sp pc ? @sp pc ? pc+d:8 2 6 jsr @rn spC2 ? sp pc ? @sp pc ? rn16 2 6 jsr @aa:16 spC2 ? sp pc ? @sp pc ? aa:16 4 8 456 table a.1 instruction set (cont) addressing mode/ instruction length (bytes) condition code mnemonic operand size operation #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied ihnzvc no. of states jsr @@aa:8 spC2 ? sp pc ? @sp pc ? @aa:8 2 8 rts pc ? @sp sp+2 ? sp 2 8 rte ccr ? @sp sp+2 ? sp pc ? @sp sp+2 ? sp 2 10 sleep transit to power-down state 2 2 ldc #xx:8, ccr b #xx:8 ? ccr 2 2 ldc rs, ccr b rs8 ? ccr 2 2 stc ccr, rd b ccr ? rd8 2 2 andc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 xorc #xx:8, ccr b ccr ? #xx:8 ? ccr 2 2 nop pc ? pc+2 2 2 notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 (n = value of r4l). (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. 457 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 458 table a.2 operation code map " # " # high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * # note: * the push and pop instructions are identical in machine language to mov instructions. bit-manipulation instructions 459 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a-3 indicates the number of states required for each cycle (instruction fetch, data read/write, etc.) in instruction execution, and table a-4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 460 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip module is accessed. see 2.9.1, notes on data access for details. 461 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 462 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bclr bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 463 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bset bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 note: n: initial value in r4l. the source and destination operands are accessed n + 1 times each. 464 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 21 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 21 mov.b rs, @Crd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 21 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 21 mov.w rs, @Crd 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rs 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 465 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shll shll.b rd 1 shal shal.b rd 1 shar shar.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 466 appendix b on-chip registers b.1 i/o registers (1) address register bit namesmodule name module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'a0 scr1 snc1 snc0 cks3 cks2 cks1 cks0 sci1 h'a1 scsr1 sol orer stf h'a2 sdru sdru7 sdru6 sdru5 sdru4 sdru3 sdru2 sdru1 sdru0 h'a3 sdrl sdrl7 sdrl6 sdrl5 sdrl4 sdrl3 sdrl2 sdrl1 sdrl0 h'a4 star sta4 sta3 sta2 sta1 sta0 sci2 h'a5 edar eda4 eda3 eda2 eda1 eda0 h'a6 scr2 gap1 gap0 cks2 cks1 cks0 h'a7 scsr2 sol orer wt abt stf h'a8 smr com chr pe pm stop mp cks1 cks0 sci3 h'a9 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 h'aa scr3 tie rie te re mpie teie cke1 cke0 h'ab tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 h'ac ssr tdre rdrf oer fer per tend mpbr mpbt h'ad rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 h'ae h'af h'b0 tma tma7 tma6 tma5 tma3 tma2 tma1 tma0 timer a h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'b2 tmb tmb7 tmb2 tmb1 tmb0 timer b h'b3 tcb/tlb tcb7/ tlb7 tcb6/ tlb6 tcb5/ tlb5 tcb4/ tlb4 tcb3/ tlb3 tcb2/ tlb2 tcb1/ tlb1 tcb0/ tlb0 h'b4 tmc tmc7 tmc6 tmc5 tmc2 tmc1 tmc0 timer c h'b5 tcc/tlc tcc7/ tlc7 tcc6/ tlc6 tcc5/ tlc5 tcc4/ tlc4 tcc3/ tlc3 tcc2/ tlc2 tcc1/ tlc1 tcc0/ tlc0 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 notation: sci1: serial communication interface 1 sci2: serial communication interface 2 sci3: serial communication interface 3 467 address register bit namesmodule name module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 timer f h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc tmg ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 timer g h'bd icrgf icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgf0 h'be icrgr icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgr0 h'bf h'c0 lpcr dts1 dts0 cmx sgx sgs3 sgs2 sgs1 sgs0 lcd h'c1 lcr psw act disp cks3 cks2 cks1 cks0 controller/ driver h'c2 h'c3 h'c4 amr cks trge ch3 ch2 ch1 ch0 a/d h'c5 adrr adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 converter h'c6 adsr adsf h'c7 h'c8 pmr1 irq3 irq2 irq1 pwm tmig tmofh tmofl tmow i/o ports h'c9 pmr2 pof2 ncs irq0 pof1 ud irq4 h'ca pmr3 cs strb so2 si2 sck2 so1 si1 sck1 h'cb pmr4 nmod7 nmod6 nmod5 nmod4 nmod3 nmod2 nmod1 nmod0 h'cc pmr5 wkp 7 wkp 6 wkp 5 wkp 4 wkp 3 wkp 2 wkp 1 wkp 0 h'cd h'ce h'cf rlctr rlct1 rlct0 h'd0 pwcr pwcr0 14-bit h'd1 pwdru pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 pwm h'd2 pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 h'd3 h'd4 pdr1 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 i/o ports h'd5 pdr2 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 h'd6 pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 h'd7 pdr4 p4 3 p4 2 p4 1 p4 0 h'd8 pdr5 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 h'd9 pdr6 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 468 address register bit namesmodule name module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'da pdr7 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 i/o ports h'db pdr8 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 h'dc pdr9 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 h'dd pdra pa 3 pa 2 pa 1 pa 0 h'de pdrb pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 h'df pdrc pc 3 pc 2 pc 1 pc 0 h'e0 pucr1 pucr1 7 pucr1 6 pucr1 5 pucr1 4 pucr1 3 pucr1 2 pucr1 1 pucr1 0 h'e1 pucr3 pucr3 7 pucr3 6 pucr3 5 pucr3 4 pucr3 3 pucr3 2 pucr3 1 pucr3 0 h'e2 pucr5 pucr5 7 pucr5 6 pucr5 5 pucr5 4 pucr5 3 pucr5 2 pucr5 1 pucr5 0 h'e3 pucr6 pucr6 7 pucr6 6 pucr6 5 pucr6 4 pucr6 3 pucr6 2 pucr6 1 pucr6 0 h'e4 pcr1 pcr1 7 pcr1 6 pcr1 5 pcr1 4 pcr1 3 pcr1 2 pcr1 1 pcr1 0 h'e5 pcr2 pcr2 7 pcr2 6 pcr2 5 pcr2 4 pcr2 3 pcr2 2 pcr2 1 pcr2 0 h'e6 pcr3 pcr3 7 pcr3 6 pcr3 5 pcr3 4 pcr3 3 pcr3 2 pcr3 1 pcr3 0 h'e7 pcr4 pcr4 2 pcr4 1 pcr4 0 h'e8 pcr5 pcr5 7 pcr5 6 pcr5 5 pcr5 4 pcr5 3 pcr5 2 pcr5 1 pcr5 0 h'e9 pcr6 pcr6 7 pcr6 6 pcr6 5 pcr6 4 pcr6 3 pcr6 2 pcr6 1 pcr6 0 h'ea pcr7 pcr7 7 pcr7 6 pcr7 5 pcr7 4 pcr7 3 pcr7 2 pcr7 1 pcr7 0 h'eb pcr8 pcr8 7 pcr8 6 pcr8 5 pcr8 4 pcr8 3 pcr8 2 pcr8 1 pcr8 0 h'ec pcr9 pcr9 7 pcr9 6 pcr9 5 pcr9 4 pcr9 3 pcr9 2 pcr9 1 pcr9 0 h'ed pcra pcra 3 pcra 2 pcra 1 pcra 0 h'ee h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson system h'f1 syscr2 nesel dton mson sa1 sa0 control h'f2 iegr ieg4 ieg3 ieg2 ieg1 ieg0 h'f3 ienr1 ienta iens1 ienwp ien4 ien3 ien2 ien1 ien0 h'f4 ienr2 iendt ienad iens2 ientg ientfh ientfl ientc ientb h'f5 h'f6 irr1 irrta irrs1 irri4 irri3 irri2 irri1 irri0 system h'f7 irr2 irrdt irrad irrs2 irrtg irrtfh irrtfl irrtc irrtb control h'f8 h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system control 469 address register bit namesmodule name module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'fa h'fb h'fc h'fd h'fe h'ff h'ff 470 b.2 i/o registers (2) tmc?imer mode register c h'b4 timer c register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 10 1 1 00 1 10 1 internal clock: internal clock: internal clock: external event (tmic): /8192 /2048 /512 /64 /16 /4 /4 rising or falling edge w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * auto-reload function select interval function selected auto-reload function selected 0 1 f f f f f f f 471 scr1serial control register 1 h'a0 sci1 bit initial value read/write 7 snc1 0 r/w 6 snc0 0 r/w 5 0 r/w 4 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w operation mode select clock source select 0 clock source is prescaler s, and pin sck is output pin 1 clock source is external clock, and pin sck is input pin 0 8-bit synchronous transfer mode 16-bit synchronous transfer mode 1 0 1 0 1 continuous clock output mode reserved clock select (cks2 to cks0) bit 2 cks2 cks1 cks0 bit 1 bit 0 0 /1024 /256 1 1 0 /64 /32 1 /16 100 1 /8 00 /4 10 1 /2 = 5 mhz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 mhz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s synchronous serial clock cycle 1 1 prescaler division ff f f f f f f f f 472 scsr1serial control/status register 1 h'a1 sci1 bit initial value read/write 7 1 6 sol 0 r/w 5 orer 0 r/(w) 4 0 3 0 0 stf 0 r/w 2 0 1 0 extended data bit overrun error flag 0 read 1 * start flag 0 indicates that transfer is stopped invalid 1 read write read write indicates transfer in progress starts a transfer operation note: only a write of 0 for flag clearing is possible. * 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] set if a clock pulse is input after transfer is complete, when an external clock is used so pin output level is low 1 write so pin output level changes to low 1 read so pin output level is high 1 write so pin output level changes to high 1 473 sdruserial data register u h'a2 sci1 bit initial value read/write 7 sdru7 not fixed r/w 6 sdru6 not fixed r/w 5 sdru5 not fixed r/w 4 sdru4 not fixed r/w 3 sdru3 not fixed r/w 0 sdru0 not fixed r/w 2 sdru2 not fixed r/w 1 sdru1 not fixed r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: not used upper 8 bits of data sdrlserial data register l h'a3 sci1 bit initial value read/write 7 sdrl7 not fixed r/w 6 sdrl6 not fixed r/w 5 sdrl5 not fixed r/w 4 sdrl4 not fixed r/w 3 sdrl3 not fixed r/w 0 sdrl0 not fixed r/w 2 sdrl2 not fixed r/w 1 sdrl1 not fixed r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: 8-bit data lower 8 bits of data starstart address register h'a4 sci2 bit initial value read/write 7 1 6 1 5 1 4 sta4 0 r/w 3 sta3 0 r/w 0 sta0 0 r/w 2 sta2 0 r/w 1 sta1 0 r/w transfer start address in range from h'ff80 to h'ff9f 474 edarend address register h'a5 sci2 bit initial value read/write 7 1 6 1 5 1 4 eda4 0 r/w 3 eda3 0 r/w 0 eda0 0 r/w 2 eda2 0 r/w 1 eda1 0 r/w transfer end address in range from h'ff80 to h'ff9f scr2serial control register 2 h'a6 sci2 bit initial value read/write 7 1 6 1 5 1 4 gap1 0 r/w 3 gap0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w gap select 0 no gaps between bytes a gap of 8 clock cycles is inserted between bytes 1 0 1 0 1 a gap of 24 clock cycles is inserted between bytes a gap of 56 clock cycles is inserted between bytes clock select (cks2 to cks0) bit 2 cks2 cks1 cks0 bit 1 bit 0 0 sck output 1 1 0 1 100 1 00 10 1 sck input = 5 mhz 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 mhz 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s serial clock cycle pin sck /256 /64 /32 /16 /8 /4 /2 prescaler division 2 2 prescaler s external clock clock source 2 ff f f f f f f f 475 scsr2serial control/status register 2 h'a7 sci2 bit initial value read/write 7 1 6 1 5 1 4 sol 0 r/w 3 orer 0 r/(w) 0 stf 0 r/w 2 wt 0 r/(w) 1 abt 0 r/(w) extended data bit abort flag * start flag 0 indicates that transfer is stopped stops a transfer operation 1 read write read write indicates transfer in progress or waiting for cs input starts a transfer operation note: only a write of 0 for flag clearing is possible. * ** wait flag overrun error flag 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] when cs goes high during a transfer 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] an attempt was made to read or write the (32-byte) serial data buffer during a transfer or while waiting for cs input 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] set if a clock pulse is input after transfer is complete, when an external clock is used 0 read 1 so pin output level is low 2 write so pin output level changes to low 2 read so pin output level is high 2 write so pin output level changes to high 2 476 smrserial mode register h'a8 sci3 bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w parity enable 0 parity bit adding and checking disabled 1 parity bit adding and checking enabled clock select 0, 1 0 0 1 10 1 clock /4 clock /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity character length 0 8-bit data 1 7-bit data communication mode 0 asynchronous mode 1 synchronous mode f f f f brrbit rate register h'a9 sci3 bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w 477 scr3serial control register 3 h'aa sci3 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable cke1 bit 1 cke0 bit 0 description transmit end interrupt enable 0 transmit end interrupt (tei) disabled communication mode clock source sck pin function 3 1 transmit end interrupt (tei) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (ordinary receive operation) [clearing condition] multiprocessor bit receives a data value of 1 1 multiprocessor interrupt request enabled until a multiprocessor bit value of 1 is received, the receive data full interrupt (rxi) and receive error interrupt (eri) are disabled, and serial status register (ssr) flags rdrf, fer, and oer are not set. 0 0 asynchronous internal clock i/o port synchronous internal clock serial clock output 1 asynchronous internal clock clock output synchronous reserved reserved (do not set this combination) 1 0 asynchronous external clock clock input synchronous external clock serial clock input 1 asynchronous reserved reserved synchronous reserved (do not set this combination) reserved (do not set this combination) transmit enable 0 transmit operation disabled (txd is a general i/o port) 1 transmit operation enabled (txd is the transmit data pin) receive enable 0 receive operation disabled (rxd is a general i/o port) 1 receive operation enabled (rxd is the receive data pin) receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 478 tdrtransmit data register h'ab sci3 bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w data to be transferred to tsr 479 ssrserial status register h'ac sci3 bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 oer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r * * * * * note: only a write of 0 for flag clearing is possible. * 0 the multiprocessor bit in transmit data is 0 multiprocessor bit transmit 1 the multiprocessor bit in transmit data is 1 0 indicates reception of data in which the multiprocessor bit is 0 multiprocessor bit receive 1 indicates reception of data in which the multiprocessor bit is 1 0 indicates that transmission is in progress transmit end [clearing conditions] after reading tdre = 1, cleared by writing 0 to tdre. when data is written to tdr by an instruction. 1 indicates that a transmission has ended [setting conditions] when bit te in serial control register 3 (scr3) is 0. if tdre is set to 1 when the last bit of a transmitted character is sent. 0 indicates that data receiving is in progress or has been completed parity error [clearing conditions] after reading per = 1, cleared by writing 0 1 indicates that a parity error occurred in data receiving [setting conditions] when the sum of 1s in received data plus the parity bit does not match the parity mode bit (pm) setting in the serial mode register (smr) 0 indicates that data receiving is in progress or has been completed framing error [clearing conditions] after reading fer = 1, cleared by writing 0 1 indicates that a framing error occurred in data receiving [setting conditions] the stop bit at the end of receive data is checked and found to be 0 0 indicates that data receiving is in progress or has been completed overrun error [clearing conditions] after reading oer = 1, cleared by writing 0 1 indicates that an overrun error occurred in data receiving [setting conditions] when data receiving is completed while rdrf is set to 1 0 indicates there is no receive data in rdr receive data register full [clearing conditions] after reading rdrf = 1, cleared by writing 0. when data is read from rdr by an instruction. 1 indicates that there is receive data in rdr [setting conditions] when receiving ends normally, with receive data transferred from rsr to rdr 0 indicates that transmit data written to tdr has not been transferred to tsr transmit data register empty [clearing conditions] after reading tdre = 1, cleared by writing 0. when data is written to tdr by an instruction. 1 indicates that no transmit data has been written to tdr, or the transmit data written to tdr has been transferred to tsr [setting conditions] when bit te in serial control register 3 (scr3) is 0. when data is transferred from tdr to tsr. 480 rdrreceive data register h'ad sci3 bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r tmatimer mode register a h'b0 timer a bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 clock output select 0 /32 /16 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period /8192 /4096 /2048 /512 /256 /128 /32 /8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base function 0 0 1 /8 /4 10 1 1 00 1 10 1 /32 w /16 w /8 w /4 w 3 tma3 0 r/w f f f f f f f f f f f f f f f f 481 tcatimer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value tmbtimer mode register b h'b2 timer b bit initial value read/write 7 tmb7 0 r/w 6 1 5 1 3 1 0 tmb0 0 r/w 2 tmb2 0 r/w 1 tmb1 0 r/w 4 1 auto-reload function select clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 10 1 1 00 1 10 1 internal clock: internal clock: internal clock: external event (tmib): /8192 /2048 /512 /256 /64 /16 /4 rising or falling edge 0 interval timer function selected 1 auto-reload function selected f f f f f f f 482 tcbtimer counter b h'b3 timer b bit initial value read/write 7 tcb7 0 r 6 tcb6 0 r 5 tcb5 0 r 4 tcb4 0 r 3 tcb3 0 r 0 tcb0 0 r 2 tcb2 0 r 1 tcb1 0 r count value tlbtimer load register b h'b3 timer b bit initial value read/write 7 tlb7 0 w 6 tlb6 0 w 5 tlb5 0 w 4 tlb4 0 w 3 tlb3 0 w 0 tlb0 0 w 2 tlb2 0 w 1 tlb1 0 w reload value 483 tmctimer mode register c h'b4 timer c bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 auto-reload function select clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 10 1 1 00 1 10 1 internal clock: internal clock: internal clock: external event (tmic): /8192 /2048 /512 /64 /16 /4 /4 rising or falling edge 0 interval timer function selected 1 auto-reload function selected w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down operation is hardware-controlled by input at the ud pin. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * note: don? care * f f f f f f f tcctimer counter c h'b5 timer c bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r count value 484 tlctimer load register c h'b5 timer c bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w reload value tcrftimer control register f h'b6 timer f bit initial value read/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 3 toll 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w toggle output level h clock select l 0 1 00 1 10 1 internal clock: internal clock: internal clock: internal clock: /32 /16 /4 note: don? care * external event (tmif): rising or falling edge ** /2 toggle output level l 0 low level 1 high level clock select h 0 1 00 1 10 1 internal clock: internal clock: internal clock: internal clock: /32 /16 /4 16-bit mode selected. tcfl overflow signals are counted. ** /2 0 low level 1 high level f f f f f f f f 485 tcsrftimer control/status register f h'b7 timer f bit initial value read/write 7 ovfh 0 r/(w) 6 cmfh 0 r/(w) 5 ovieh 0 r/w 4 cclrh 0 r/w 3 ovfl 0 r/(w) 0 cclrl 0 r/w 2 cmfl 0 r/(w) 1 oviel 0 r/w timer overflow flag h timer overflow interrupt enable l 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] when the value of tcfh goes from h'ff to h'00 note: only a write of 0 for flag clearing is possible. * 0 tcfl overflow interrupt disabled 1 tcfl overflow interrupt enabled ** ** timer overflow interrupt enable h compare match flag h 0 [clearing condition] after reading cmfh = 1, cleared by writing 0 to cmfh 1 [setting condition] when the tcfh value matches the ocrfh value 0 tcfh overflow interrupt disabled 1 tcfh overflow interrupt enabled counter clear h 0 16-bit mode: 8-bit mode: 1 tcf clearing by compare match disabled tcfh clearing by compare match disabled 16-bit mode: 8-bit mode: tcf clearing by compare match enabled tcfh clearing by compare match enabled timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] when the value of tcfl goes from h'ff to h'00 compare match flag l 0 [clearing condition] after reading cmfl = 1, cleared by writing 0 to cmfl 1 [setting condition] when the tcfl value matches the ocrfl value counter clear l 0 tcfl clearing by compare match disabled 1 tcfl clearing by compare match enabled 486 tcfh8-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value tcfl8-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value ocrfhoutput compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w ocrfloutput compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w 487 tmgtimer mode register g h'bc timer g bit initial value read/write 7 ovfh 0 r/(w) 6 ovfl 0 r/(w) 5 ovie 0 r/w 4 iiegs 0 r/w 3 cclr1 0 r/w 0 cks0 0 r/w 2 cclr0 0 r/w 1 cks1 0 r/w timer overflow flag h 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] when the value of tcg goes from h'ff to h'00 note: only a write of 0 for flag clearing is possible. * ** timer overflow interrupt enable timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] when the value of tcg goes from h'ff to h'00 0 tcg overflow interrupt disabled 1 tcg overflow interrupt enabled input capture interrupt edge select 0 interrupts are requested at the rising edge of the input capture signal 1 interrupts are requested at the falling edge of the input capture signal clock select 0 internal clock: internal clock: 0 1 internal clock: internal clock: 10 1 /64 /32 /2 /2 w counter clear 0 tcg is not cleared tcg is cleared at the falling edge of the input capture signal 0 1 tcg is cleared at the rising edge of the input capture signal tcg is cleared at both edges of the input capture signal 10 1 f f f f 488 icrgfinput capture register gf h'bd timer g bit initial value read/write 7 icrgf7 0 r 6 icrgf6 0 r 5 icrgf5 0 r 4 icrgf4 0 r 3 icrgf3 0 r 0 icrgf0 0 r 2 icrgf2 0 r 1 icrgf1 0 r icrgrinput capture register gr h'be timer g bit initial value read/write 7 icrgr7 0 r 6 icrgr6 0 r 5 icrgr5 0 r 4 icrgr4 0 r 3 icrgr3 0 r 0 icrgr0 0 r 2 icrgr2 0 r 1 icrgr1 0 r 489 lpcrlcd port control register h'c0 lcd controller/driver bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 3 sgs3 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w segment driver select 4 sgx 0 r/w sgx bit 4 0 sgs3 bit 3 0 sgs2 bit 2 0 sgs1 bit 1 0 sgs0 bit 0 0 seg to seg 40 37 port seg to seg 36 33 port seg to seg 32 29 port seg to seg 28 25 port seg to seg 24 21 port seg to seg 20 17 port seg to seg 16 13 port seg to seg 12 9 port seg to seg 8 5 port seg to seg 4 1 port remarks (initial value) 1 seg seg port port port port port port port port 1 0 seg seg seg port port port port port port port 1 seg seg seg seg port port port port port port 1 0 0 seg seg seg seg seg port port port port port 1 seg seg seg seg seg seg port port port port 1 0 seg seg seg seg seg seg seg port port port 1 seg seg seg seg seg seg seg seg port port 1 0 seg seg seg seg seg seg seg seg seg port 1 seg seg seg seg seg seg seg seg seg seg 1 0000 external segment expansion port port port port port port port port port 1 seg port port port port port port port port 1 0 seg seg port port port port port port port 1 seg seg seg port port port port port port 1 0 0 seg seg seg seg port port port port port 1 seg seg seg seg seg port port port port 1 0 seg seg seg seg seg seg port port port 1 seg seg seg seg seg seg seg port port 1 0 seg seg seg seg seg seg seg seg port 1 seg seg seg seg seg seg seg seg seg functions of pins seg to seg 1 40 external segment expansion external segment expansion external segment expansion external segment expansion external segment expansion external segment expansion external segment expansion external segment expansion external segment expansion duty and common function select dts1 bit 7 0 dts0 bit 6 0 cmx bit 5 0 duty static common driver com other uses com , com , and com usable as ports 1321 1 com to com com , com , and com output the same waveform as com 44 1 32 1 0 1 0 1/2 duty com , com com and com usable as ports 243 1 com to com com outputs the same waveform as com , and com the same waveform as com 44 1 32 1 1 1 0 0 1/3 duty com usable as port 4 1 com to com com outputs a non-select waveform 44 1 1 1 0 1/4 duty 1 com to com 41 com to com 31 0 pins seg to seg pins cl , cl , do, and m 1 40 1 37 2 expansion signal select ** ** 490 lcrlcd control register h'c1 lcd controller/driver bit initial value read/write 7 1 6 psw 0 r/w 5 act 0 r/w 4 disp 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w frame frequency select bit 3 0 bit 2 * clock cks3 cks2 0 cks1 0 1 cks0 bit 1 bit 0 /2 1 * 0 /2 /4 1 1 0 /8 /16 1 /32 100 1 /64 1 00 /128 10 1 /256 w w w 128 hz (initial value) = 5 mhz 64 hz 32 hz 610 hz 305 hz 153 hz 76.3 hz 38.1 hz = 625 hz 610 hz 305 hz 153 hz 76.3 hz 38.1 hz frame frequency display active 0 lcd controller/driver operation stopped 1 lcd controller/driver operational display data control 0 blank data displayed 1 lcd ram data displayed power switch 0 lcd power supply resistive voltage divider off 1 lcd power supply resistive voltage divider on note: don? care * f f f f f f f f f f f f f 491 amra/d mode register h'c4 a/d converter bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel ch3 ch2 0 ch1 ch0 bit 1 bit 0 0an 1 1 0 1 100 1 1 00 10 1 external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg 5 1 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 ** 100 1 10 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 31 s = 2 mhz 15.5 s 12.4 s = 5 mhz * conversion time notes: 1 * 1. don? care operation is not guaranteed if the conversion time is less than 12.4 s. set bit 7 for a value of at least 12.4 s. ff f f 492 adrra/d result register h'c5 a/d converter bit initial value read/write 7 adr7 not fixed r 6 adr6 not fixed r 5 adr5 not fixed r 4 adr4 not fixed r 3 adr3 not fixed r 0 adr0 not fixed r 2 adr2 not fixed r 1 adr1 not fixed r a/d conversion result adsra/d start register h'c6 a/d converter bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 a/d status flag 0 read 1 indicates the completion of a/d conversion write stops a/d conversion read indicates a/d conversion in progress write starts a/d conversion 493 pmr1port mode register 1 h'c8 i/o ports bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 4 pwm 0 r/w 3 tmig 0 r/w 0 tmow 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w p1 /tmow pin function switch 0 functions as p1 i/o pin 1 functions as tmow output pin p1 /tmig pin function switch 0 functions as p1 i/o pin 1 functions as tmig input pin p1 /tmofl pin function switch 0 functions as p1 i/o pin 1 functions as tmofl output pin p1 /tmofh pin function switch 0 functions as p1 i/o pin 1 functions as tmofh output pin p1 /pwm pin function switch 0 functions as p1 i/o pin 1 functions as pwm output pin p1 /irq /tmib pin function switch p1 /irq /tmic pin function switch 1 0 functions as p1 i/o pin 1 functions as irq /tmib input pin 0 functions as p1 i/o pin 1 functions as irq /tmic input pin p1 /irq /tmif pin function switch 1 0 functions as p1 i/o pin 1 functions as irq /tmif input pin 0 3 1 2 4 5 6 7 0 3 1 2 4 5 6 7 1 2 3 1 2 3 494 pmr2port mode register 2 h'c9 i/o ports bit initial value read/write 7 1 6 1 5 pof2 0 r/w 4 ncs 0 r/w 3 irq0 0 r/w 0 irq4 0 r/w 2 pof1 0 r/w 1 ud 0 r/w p2 /ud pin function switch 0 functions as p2 i/o pin 1 functions as ud input pin p3 /so pin pmos control 0 cmos output 1 nmos open-drain output tmig noise canceller select 0 noise canceller function not selected 1 noise canceller function selected p3 /so pin pmos control p2 /irq /adtrg pin function switch 1 0 cmos output 1 nmos open-drain output 0 functions as p2 i/o pin 1 functions as irq /adtrg input pin 1 2 5 0 1 0 2 4 4 1 p4 /irq pin function switch 1 0 functions as p4 i/o pin 1 functions as irq input pin 3 3 0 0 495 pmr3port mode register 3 h'ca i/o ports bit initial value read/write 7 cs 0 r/w 6 strb 0 r/w 5 so2 0 r/w 4 si2 0 r/w 3 sck2 0 r/w 0 sck 0 r/w 2 so1 0 r/w 1 si1 0 r/w p3 /sck pin function switch 0 functions as p3 i/o pin 1 functions as sck i/o pin p3 /sck pin function switch 0 functions as p3 i/o pin 1 functions as sck i/o pin p3 /si pin function switch 0 functions as p3 i/o pin 1 functions as si input pin p3 /so pin function switch 0 functions as p3 i/o pin 1 functions as so output pin p3 /si pin function switch 0 functions as p3 i/o pin 1 functions as si input pin p3 /so pin function switch p3 /strb pin function switch 1 0 functions as p3 i/o pin 1 functions as so output pin 0 functions as p3 i/o pin 1 functions as strb output pin p3 /cs pin function switch 1 0 functions as p3 i/o pin 1 functions as cs input pin 0 3 1 2 4 5 6 7 0 3 1 2 4 5 6 7 2 2 1 1 1 1 1 1 2 2 2 2 1 496 pmr4port mode register 4 h'cb i/o ports bit initial value read/write 7 nmod7 0 r/w 6 nmod6 0 r/w 5 nmod5 0 r/w 4 nmod4 0 r/w 3 nmod3 0 r/w 0 nmod0 0 r/w 2 nmod2 0 r/w 1 nmod1 0 r/w 0 p2 has cmos output 1 p2 has nmos open-drain output n n pmr5port mode register 5 h'cc i/o ports bit initial value read/write 7 wkp7 0 r/w 6 wkp6 0 r/w 5 wkp5 0 r/w 4 wkp4 0 r/w 3 wkp3 0 r/w 0 wkp0 0 r/w 2 wkp2 0 r/w 1 wkp1 0 r/w 0 functions as p5 i/o pin 1 functions as wkp input pin n n p5 /wkp /seg pin function switch n n n + 1 rlctrlcd ram relocation register h'cf bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 rlct0 0 r/w 2 1 1 rlct1 0 r/w 497 pwcrpwm control register h'd0 14-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 1 clock select 0 the input clock is /2 (t = 2/ ). the conversion period is 16,384/ , with a minimum modulation width of 1/ 1 the input clock is /4 (t = 4/ ). the conversion period is 32,768/ , with a minimum modulation width of 2/ * * note: t? period of pwm input clock * ff f f f f f f f f pwdrupwm data register u h'd1 14-bit pwm bit initial value read/write 7 1 6 1 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w upper 6 bits of data for generating pwm waveform pwdru5 pwdru4 pwdru3 pwdru0 pwdru2 pwdur1 pwdrlpwm data register l h'd2 14-bit pwm bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm waveform pwdrl5 pwdrl4 pwdrl3 pwdrl0 pwdrl2 pwdrl1 pwdrl6 pwdrl7 498 pdr1port data register 1 h'd4 i/o ports bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 76543 0 21 pdr2port data register 2 h'd5 i/o ports bit initial value read/write 7 p2 0 r/w 6 p2 0 r/w 5 p2 0 r/w 4 p2 0 r/w 3 p2 0 r/w 0 p2 0 r/w 2 p2 0 r/w 1 p2 0 r/w 76543 0 21 pdr3port data register 3 h'd6 i/o ports bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 76543 0 21 pdr4port data register 4 h'd7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 30 21 pdr5port data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 499 pdr6port data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 pdr7port data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 30 21 4 5 6 7 pdr8port data register 8 h'db i/o ports bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 30 21 4 5 6 7 pdr9port data register 9 h'dc i/o ports bit initial value read/write 7 p9 0 r/w 6 p9 0 r/w 5 p9 0 r/w 4 p9 0 r/w 3 p9 0 r/w 0 p9 0 r/w 2 p9 0 r/w 1 p9 0 r/w 30 21 4 5 6 7 pdraport data register a h'dd i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 30 21 500 pdrbport data register b h'de i/o ports bit initial value read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 30 21 4 5 6 7 pdrcport data register c h'df i/o ports bit initial value read/write 7 6 5 4 3 pc r 0 pc r 2 pc r 1 pc r 30 21 pucr1port pull-up control register 1 h'e0 i/o ports bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 30 21 4 5 6 7 pucr3port pull-up control register 3 h'e1 i/o ports bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 30 21 4 5 6 7 pucr5port pull-up control register 5 h'e2 i/o ports bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 30 21 4 5 6 7 501 pucr6port pull-up control register 6 h'e3 i/o ports bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 30 21 4 5 6 7 pcr1port control register 1 h'e4 i/o ports bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w port 1 input/output select 0 input pin 1 output pin 76543 0 21 pcr2port control register 2 h'e5 i/o ports bit initial value read/write 7 pcr2 0 w 6 pcr2 0 w 5 pcr2 0 w 4 pcr2 0 w 3 pcr2 0 w 0 pcr2 0 w 2 pcr2 0 w 1 pcr2 0 w port 2 input/output select 0 input pin 1 output pin 76543 0 21 502 pcr3port control register 3 h'e6 i/o ports bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 76543 0 21 pcr4port control register 4 h'e7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 21 pcr5port control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21 503 pcr6port control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 pcr7port control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 76543 0 21 pcr8port control register 8 h'eb i/o ports bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w port 8 input/output select 0 input pin 1 output pin 76543 0 21 504 pcr9port control register 9 h'ec i/o ports bit initial value read/write 7 pcr9 0 w 6 pcr9 0 w 5 pcr9 0 w 4 pcr9 0 w 3 pcr9 0 w 0 pcr9 0 w 2 pcr9 0 w 1 pcr9 0 w port 9 input/output select 0 input pin 1 output pin 76543 0 21 pcraport control register a h'ed i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 w 0 pcra 0 w 2 pcra 0 w 1 pcra 0 w 30 21 port a input/output select 0 input pin 1 output pin 505 syscr1system control register 1 h'f0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 1 2 1 1 1 4 sts0 0 r/w software standby 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode. 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 32,768 states wait time = 65,536 states 10 1 1 * wait time = 131,072 states low speed on flag 0 the cpu operates on the system clock ( ) 1 the cpu operates on the subclock ( ) sub * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode. when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode. when a sleep instruction is executed in subactive mode, a transition is made to watch mode. note: don? care * f f 506 syscr2system control register 2 h'f1 system control bit initial value read/write 7 1 6 1 5 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 0 r/w direct transfer on flag 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. 1 when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. subactive mode clock select 0 /8 /4 0 1 1 /2 * w w w noise elimination sampling frequency select 0 sampling rate is /16 1 sampling rate is /4 osc osc when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1. medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode note: don? care * f f f f f 507 iegrirq edge select register h'f2 system control bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w irq edge select 0 falling edge of irq pin input is detected 1 rising edge of irq pin input is detected 0 0 0 irq edge select 0 falling edge of irq /tmib pin input is detected 1 rising edge of irq /tmib pin input is detected 1 1 1 irq edge select 0 falling edge of irq /tmic pin input is detected 1 rising edge of irq /tmic pin input is detected 2 2 2 irq edge select 0 falling edge of irq /tmif pin input is detected 1 rising edge of irq /tmif pin input is detected 3 3 3 irq edge select 0 falling edge of irq /adtrg pin input is detected 1 rising edge of irq /adtrg pin input is detected 4 4 4 508 ienr1interrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 iens1 0 r/w 5 ienwp 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w irq to irq interrupt enable 0 disables interrupt request irq 1 4 n 0 enables interrupt request irq n wakeup interrupt enable 0 disables interrupt requests from wkp to wkp 1 70 enables interrupt requests from wkp to wkp 70 sci1 interrupt enable 0 disables sci1 interrupts 1 enables sci1 interrupts timer a interrupt enable 0 disables timer a interrupts 1 enables timer a interrupts (n = 4 to 0) 509 ienr2interrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 iens2 0 r/w 4 ientg 0 r/w 3 ientfh 0 r/w 0 ientb 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w timer b interrupt enable 0 disables timer b interrupts 1 enables timer b interrupts timer fh interrupt enable 0 disables timer fh interrupts 1 enables timer fh interrupts timer c interrupt enable 0 disables timer c interrupts 1 enables timer c interrupts timer fl interrupt enable 0 disables timer fl interrupts 1 enables timer fl interrupts timer g interrupt enable 0 disables timer g interrupts 1 enables timer g interrupts a/d converter interrupt enable 1 0 disables sci2 interrupts 1 enables sci2 interrupts 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests direct transfer interrupt enable 1 0 disables direct transfer interrupt requests 1 enables direct transfer interrupt requests sci2 interrupt enable 510 irr1interrupt request register 1 h'f6 system control bit initial value read/write 7 irrta 0 r/w 6 irrs1 0 r/w 5 1 4 irri4 0 r/w 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w timer a interrupt request flag 0 [clearing condition] when irrta = 1, it is cleared by writing 0 1 [setting condition] when the timer a counter overflows from h'ff to h'00 note: only a write of 0 for flag clearing is possible. * ** ** sci1 interrupt request flag 0 [clearing condition] when irrs1 = 1, it is cleared by writing 0 1 [setting condition] when an sci1 transfer is completed irq to irq interrupt request flag 0 [clearing condition] when irrin = 1, it is cleared by writing 0 1 [setting condition] when pin irq is set to interrupt input and the designated signal edge is detected *** 40 n (n = 4 to 0) 511 irr2interrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 irrs2 0 r/w 4 irrtg 0 r/w 3 irrtfh 0 r/w 0 irrtb 0 r/w 2 irrtfl 0 r/w 1 irrtc 0 r/w direct transfer interrupt request flag 0 [clearing condition] 1 [setting condition] note: only a write of 0 for flag clearing is possible. * ** ** *** * when irrdt = 1, it is cleared by writing 0 a sleep instruction is executed when dton = 1 and a direct transfer is made a/d converter interrupt request flag 0 [clearing condition] 1 [setting condition] when irrad = 1, it is cleared by writing 0 when a/d conversion is completed and adsf is reset sci2 interrupt request flag 0 [clearing condition] 1 [setting condition] when irrs2 = 1, it is cleared by writing 0 when an sci2 transfer is completed or aborted timer g interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtg = 1, it is cleared by writing 0 when pin tmig is set to tmig input and the designated signal edge is detected timer fh interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtfh = 1, it is cleared by writing 0 when counter fh matches output compare register fh in 8-bit mode, or when 16-bit counter f (tcfl, tcfh) matches 16-bit output compare register f (ocrfl, ocrfh) in 16-bit mode timer fl interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtfl = 1, it is cleared by writing 0 when counter fl matches output compare register fl in 8-bit mode timer c interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtc = 1, it is cleared by writing 0 when the timer c counter overflows from h'ff to h'00 or underflows from h'00 to h'ff timer b interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtb = 1, it is cleared by writing 0 when the timer b counter overflows from h'ff to h'00 512 iwprwakeup interrupt request register h'f9 system control bit initial value read/write 7 iwpf7 0 r/w 6 iwpf6 0 r/w 5 iwpf5 0 r/w 4 iwpf4 0 r/w 3 iwpf3 0 r/w 0 iwpf0 0 r/w 2 iwpf2 0 r/w 1 iwpf1 0 r/w note: only a write of 0 for flag clearing is possible. * ** ** wakeup interrupt request flag 0 [clearing condition] when iwpfn = 1, it is cleared by writing 0 1 [setting condition] when pin wkp is set to interrupt input and a falling signal edge is detected *** * n (n = 7 to 0) 513 appendix c i/o port block diagrams c.1 block diagram of port 1 sby (low level during reset and in standby mode) pucr1 n pmr1 n pdr1 n pcr1 n internal data bus pdr1: pcr1: pmr1: pucr1: n = 5 to 7 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 v cc v cc irq n ?4 v ss p1 n figure c.1 (a) port 1 block diagram (pins p1 7 to p1 5 ) 514 sby pucr1 4 pmr1 4 pdr1 4 pcr1 4 internal data bus pwm pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 v cc pwm module p1 4 v cc v ss figure c.1 (b) port 1 block diagram (pin p1 4 ) 515 sby pucr1 3 pmr1 3 pdr1 3 pcr1 3 internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmig timer g module p1 3 v cc v cc v ss figure c.1 (c) port 1 block diagram (pin p1 3 ) 516 pucr1 n pmr1 n pdr1 n pcr1 n internal data bus tmofh (p1 ) tmofl (p1 ) pdr1: pcr1: pmr1: pucr1: n = 2, 1 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 timer f module 2 1 v cc p1 n v cc v ss sby figure c.1 (d) port 1 block diagram (pins p1 2 and p1 1 ) 517 pucr1 0 pmr1 0 pdr1 0 pcr1 0 internal data bus tmow pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 timer a module v cc p1 0 v cc v ss sby figure c.1 (e) port 1 block diagram (pin p1 0 ) 518 c.2 block diagram of port 2 pmr4 n pdr2 n pcr2 n internal data bus pdr2: pcr2: pmr4: n = 2 to 7 port data register 2 port control register 2 port mode register 4 p2 n v cc v ss sby figure c.2 (a) port 2 block diagram (pins p2 7 to p2 2 ) 519 pmr4 1 pmr2 1 pdr2 1 pcr2 1 internal data bus pdr2: pcr2: pmr2: pmr4: port data register 2 port control register 2 port mode register 2 port mode register 4 ud timer c module p2 1 v cc v ss sby figure c.2 (b) port 2 block diagram (pin p2 1 ) 520 pmr4 0 pmr2 0 pdr2 0 pcr2 0 internal data bus pdr2: pcr2: pmr2: pmr4: port data register 2 port control register 2 port mode register 2 port mode register 4 irq 4 p2 0 v cc v ss sby figure c.2 (c) port 2 block diagram (pin p2 0 ) 521 c.3 block diagram of port 3 pucr3 7 pmr3 7 pdr3 7 pcr3 7 internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 cs sci2 module v cc p3 7 v cc v ss sby figure c.3 (a) port 3 block diagram (pin p3 7 ) 522 pucr3 6 pmr3 6 pdr3 6 pcr3 6 internal data bus strb pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 sci2 module v cc p3 6 v cc v ss sby figure c.3 (b) port 3 block diagram (pin p3 6 ) 523 pmr2 5 pucr3 5 pmr3 5 pdr3 5 pcr3 5 internal data bus hzs02n so 2 pdr3: pcr3: pmr3: pmr2: pucr3: port data register 3 port control register 3 port mode register 3 port mode register 2 port pull-up control register 3 sci2 module v cc p3 5 v cc v ss sby figure c.3 (c) port 3 block diagram (pin p3 5 ) 524 pucr3 n pmr3 n pdr3 n pcr3 n internal data bus pdr3: pcr3: pmr3: pucr3: n = 1, 4 port data register 3 port control register 3 port mode register 3 port pull-up control register 3 si sci module v cc p3 n v cc v ss sby figure c.3 (d) port 3 block diagram (pins p3 4 and p3 1 ) 525 pucr3 n pmr3 n pdr3 n pcr3 n exck sck o sck i pdr3: pcr3: pmr3: pucr3: n = 3, 0 port data register 3 port control register 3 port mode register 3 port pull-up control register 3 sci module v cc p3 n v cc v ss internal data bus sby figure c.3 (e) port 3 block diagram (pins p3 3 and p3 0 ) 526 pmr2 2 pucr3 2 pmr3 2 pdr3 2 pcr3 2 internal data bus so 1 pdr3: pcr3: pmr3: pmr2: pucr3: port data register 3 port control register 3 port mode register 3 port mode register 2 port pull-up control register 3 sci1 module v cc p3 2 v cc v ss sby figure c.3 (f) port 3 block diagram (pin p3 2 ) 527 c.4 block diagram of port 4 pmr2 3 internal data bus pmr2: port mode register 2 irq 0 p4 3 figure c.4 (a) port 4 block diagram (pin p4 3 ) pdr4 2 pcr4 2 internal data bus te txd pdr4: pcr4: port data register 4 port control register 4 sci3 module p4 2 v cc v ss sby figure c.4 (b) port 4 block diagram (pin p4 2 ) 528 pdr4 1 pcr4 1 pdr4: pcr4: port data register 4 port control register 4 re rxd sci3 module p4 1 v cc v ss internal data bus sby figure c.4 (c) port 4 block diagram (pin p4 1 ) 529 pdr4 0 pcr4 0 sckie sckoe scko scki pdr4: pcr4: port data register 4 port control register 4 sci3 module p4 0 v cc v ss internal data bus sby figure c.4 (d) port 4 block diagram (pin p4 0 ) 530 c.5 block diagram of port 5 pucr5 n pmr5 n pdr5 n pcr5 n internal data bus pdr5: pcr5: pmr5: pucr5: n = 0 to 7 port data register 5 port control register 5 port mode register 5 port pull-up control register 5 wkp n v cc p5 n v cc v ss sby figure c.5 port 5 block diagram 531 c.6 block diagram of port 6 pucr6 n pdr6 n pcr6 n internal data bus pdr6: pcr6: pucr4: n = 0 to 7 port data register 6 port control register 6 port pull-up control register 6 v cc p6 n v cc v ss sby figure c.6 port 6 block diagram 532 c.7 block diagram of port 7 pdr7 n pcr7 n internal data bus pdr7: pcr7: n = 0 to 7 port data register 7 port control register 7 p7 n v cc v ss sby figure c.7 port 7 block diagram 533 c.8 block diagram of port 8 pdr8 n pcr8 n internal data bus pdr8: pcr8: n = 0 to 7 port data register 8 port control register 8 p8 n v cc v ss sby figure c.8 port 8 block diagram 534 c.9 block diagram of port 9 pdr9 n pcr9 n internal data bus pdr9: pcr9: n = 0 to 7 port data register 9 port control register 9 p9 n v cc v ss sby figure c.9 port 9 block diagram 535 c.10 block diagram of port a pdra n pcra n internal data bus pdra: pcra: n = 0 to 3 port data register a port control register a pa n v cc v ss sby figure c.10 port a block diagram 536 c.11 block diagram of port b dec internal data bus amr0 to amr3 v a/d module in pb n n = 0 to 7 figure c.11 port b block diagram c.12 block diagram of port c dec internal data bus amr0 to amr3 v a/d module in pc n n = 0 to 3 figure c-12 port c block diagram 537 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p1 7 to p1 0 high impedance retained retained high impedance * retained functions functions p2 7 to p2 0 high impedance retained retained high impedance * retained functions functions p3 7 to p3 0 high impedance retained retained high impedance * retained functions functions p4 3 to p4 0 high impedance retained retained high impedance * retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * retained functions functions p6 7 to p6 0 high impedance retained retained high impedance * retained functions functions p7 7 to p7 0 high impedance retained retained high impedance * retained functions functions p8 7 to p8 0 high impedance retained retained high impedance * retained functions functions p9 7 to p9 0 high impedance retained retained high impedance * retained functions functions pa 3 to pa 0 high impedance retained retained high impedance * retained functions functions pb 7 to pb 0 high impedance high impedance high impedance high impedance * high impedance high impedance high impedance pc 3 to pc 0 high impedance high impedance high impedance high impedance * high impedance high impedance high impedance note: * high level output when mos pull-up is in on state. 538 appendix e list of product codes table e.1 h8/3834 series product code lineup product type product code mask code package (hitachi package code) h8/3837 prom versions standard models HD6473837H hd6473837f HD6473837H hd6473837f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6473837x hd6473837x 100 pin tqfp (tfp-100b) i-spec models hd6473837d hd6473837e HD6473837Hi hd6473837fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) mask rom versions standard models hd6433837h hd6433837f hd6433837( *** )h hd6433837( *** )f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433837x hd6433837( *** )x 100 pin tqfp (tfp-100b) i-spec models hd6433837d hd6433837e hd6433837( *** )hi hd6433837( *** )fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433837l hd6433837( *** )xi 100 pin tqfp (tfp-100b) h8/3836 mask rom versions standard models hd6433836h hd6433836f hd6433836( *** )h hd6433836( *** )f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433836x hd6433836( *** )x 100 pin tqfp (tfp-100b) i-spec models hd6433836d hd6433836e hd6433836( *** )hi hd6433836( *** )fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433836l hd6433836( *** )xi 100 pin tqfp (tfp-100b) h8/3835 mask rom versions standard models hd6433835h hd6433835f hd6433835( *** )h hd6433835( *** )f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433835x hd6433835( *** )x 100 pin tqfp (tfp-100b) i-spec models hd6433835d hd6433835e hd6433835( *** )hi hd6433835( *** )fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433835l hd6433835( *** )xi 100 pin tqfp (tfp-100b) note: for mask rom versions, ( *** ) is the rom code. 539 table e.1 h8/3834 series product code lineup (cont) product type product code mask code package (hitachi package code) h8/3834 prom versions standard models hd6473834h hd6473834f hd6473834h hd6473834f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6473834x hd6473834x 100 pin tqfp (tfp-100b) i-spec models hd6473834d hd6473834e hd6473834hi hd6473834fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) mask rom versions standard models hd6433834h hd6433834f hd6433834( *** )h hd6433834( *** )f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433834x hd6433834( *** )x 100 pin tqfp (tfp-100b) i-spec models hd6433834d hd6433834e hd6433834( *** )hi hd6433834( *** )fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433834l hd6433834( *** )xi 100 pin tqfp (tfp-100b) h8/3833 mask rom versions standard models hd6433833h hd6433833f hd6433833( *** )h hd6433833( *** )f 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433833x hd6433833( *** )x 100 pin tqfp (tfp-100b) i-spec models hd6433833d hd6433833e hd6433833( *** )hi hd6433833( *** )fi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433833l hd6433833( *** )xi 100 pin tqfp (tfp-100b) note: for mask rom versions, ( *** ) is the rom code. 540 table e.2 h8/3834s series product code lineup product type product code mask code package (hitachi package code) h8/3837s mask rom versions standard models hd6433837sh hd6433837sf hd6433837( *** )sh hd6433837( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433837sx hd6433837( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433837sd hd6433837se hd6433837( *** )shi hd6433837( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433837sl hd6433837( *** )sxi 100 pin tqfp (tfp-100b) h8/3836s mask rom versions standard models hd6433836sh hd6433836sf hd6433836( *** )sh hd6433836( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433836sx hd6433836( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433836sd hd6433836se hd6433836( *** )shi hd6433836( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433836sl hd6433836( *** )sxi 100 pin tqfp (tfp-100b) h8/3835s mask rom versions standard models hd6433835sh hd6433835sf hd6433835( *** )sh hd6433835( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433835sx hd6433835( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433835sd hd6433835se hd6433835( *** )shi hd6433835( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433835sl hd6433835( *** )sxi 100 pin tqfp (tfp-100b) h8/3834s mask rom versions standard models hd6433834sh hd6433834sf hd6433834( *** )sh hd6433834( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433834sx hd6433834( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433834sd hd6433834se hd6433834( *** )shi hd6433834( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433834sl hd6433834( *** )sxi 100 pin tqfp (tfp-100b) note: for mask rom versions, ( *** ) is the rom code. 541 table e.2 h8/3834s series product code lineup (cont) product type product code mask code package (hitachi package code) h8/3833s mask rom versions standard models hd6433833sh hd6433833sf hd6433833( *** )sh hd6433833( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433833sx hd6433833( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433833sd hd6433833se hd6433833( *** )shi hd6433833( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433833sl hd6433833( *** )sxi 100 pin tqfp (tfp-100b) h8/3832s mask rom versions standard models hd6433832sh hd6433832sf hd6433832( *** )sh hd6433832( *** )sf 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433832sx hd6433832( *** )sx 100 pin tqfp (tfp-100b) i-spec models hd6433832sd hd6433832se hd6433832( *** )shi hd6433832( *** )sfi 100 pin qfp (fp-100b) 100 pin qfp (fp-100a) hd6433832sl hd6433832( *** )sxi 100 pin tqfp (tfp-100b) note: for mask rom versions, ( *** ) is the rom code. 542 appendix f package dimensions dimensional drawings of h8/3834 series packages fp-100b, fp-100a, and tfp-100b are shown in figures f.1, f.2, and f.3 below. 0.10 16.0 0.3 1.0 0.5 0.2 16.0 0.3 3.05 max 75 51 50 26 1 25 76 100 14 0 ?8 0.5 0.08 m 0.22 0.05 2.70 0.17 0.05 0.12 +0.13 ?.12 1.0 0.20 0.04 0.15 0.04 unit: mm dimension including the plating thickness base material dimension figure f.1 fp-100b package dimensions 543 0.13 m 0 ?10 0.32 0.08 0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 80 51 50 31 30 1 100 81 18.8 0.4 14 0.15 0.65 2.70 2.4 0.20 +0.10 ?.20 0.58 0.83 0.30 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension figure f.2 fp-100a package dimensions 544 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max 0.17 0.05 0 ?8 75 51 125 76 100 26 50 m 0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 unit: mm dimension including the plating thickness base material dimension figure f.3 tfp-100b package dimensions note: in case of inconsistencies arising within figures, dimensional drawings listed in the hitachi semiconductor packages manual take precedence and are considered correct. h8s/3834 series hardware manual publication date: 1st edition, march 1993 5th edition, september 1997 published by: semiconductor and ic div. hitachi, ltd. edited by: technical documentation center hitachi microcomputer system ltd. copyright ?hitachi, ltd., 1993. all rights reserved. printed in japan. |
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